DS031 Datasheet, PDF (86/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Miscellaneous Timing Parameters
Table 42: Miscellaneous Timing Parameters
Description
Symbol
Time Required to Achieve LOCK
Using DLL outputs⁽¹⁾
LOCK_DLL
LOCK_DLL_60
LOCK_DLL_50_60
LOCK_DLL_40_50
LOCK_DLL_30_40
LOCK_DLL_24_30
Using CLKFX outputs
LOCK_FX_MIN
LOCK_FX_MAX
Additional lock time with
fine-phase shifting
LOCK_DLL_FINE_SHIFT
Fine-Phase Shifting
Absolute shifting range
FINE_SHIFT_RANGE
Delay Lines
Tap delay resolution
DCM_TAP_MIN
DCM_TAP_MAX
Constraints
F_CLKIN
Speed Grade
-6
-5
-4
> 60MHz
50 - 60 MHz
40 - 50 MHz
30 - 40 MHz
24 - 30 MHz
20.0
25.0
50.0
90.0
120.0
10.0
10.0
50.0
20.0
25.0
50.0
90.0
120.0
10.0
10.0
50.0
20.0
25.0
50.0
90.0
120.0
10.0
10.0
50.0
10.0
10.0
10.0
30.0
30.0
30.0
60.0
60.0
60.0
Notes:
1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. Specification also applies to PSCLK.
Units
μs
μs
μs
μs
μs
ms
ms
μs
ns
ps
ps
Frequency Synthesis
Table 43: Frequency Synthesis
Attribute
CLKFX_MULTIPLY
CLKFX_DIVIDE
Min
Max
2
32
1
32
Parameter Cross Reference
Table 44: Parameter Cross Reference
Libraries Guide
DLL_CLKOUT_{MIN|MAX}_LF
DFS_CLKOUT_{MIN|MAX}_LF
DLL_CLKIN_{MIN|MAX}_LF
DFS_CLKIN_{MIN|MAX}_LF
DLL_CLKOUT_{MIN|MAX}_HF
DFS_CLKOUT_{MIN|MAX}_HF
DLL_CLKIN_{MIN|MAX}_HF
DFS_CLKIN_{MIN|MAX}_HF
Data Sheet
CLKOUT_FREQ_{1X|2X|DV}_LF
CLKOUT_FREQ_FX_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_FX_LF
CLKOUT_FREQ_{1X|DV}_HF
CLKOUT_FREQ_FX_HF
CLKIN_FREQ_DLL_HF
CLKIN_FREQ_FX_HF
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
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