DS031 Datasheet, PDF (96/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: Pinout Information
Table 4: Virtex-II Pin Definitions (Continued)
Pin Name
Direction
Description
PROG_B
Input
Active Low asynchronous reset to configuration logic. This pin has a permanent weak
pull-up resistor.
DONE
Input/Output
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output,
this pin indicates completion of the configuration process. As an input, a Low level on
DONE can be configured to delay the start-up sequence.
M2, M1, M0
Input
Configuration mode selection.
HSWAP_EN
Input
Enable I/O pull-ups during configuration.
TCK
Input
Boundary Scan Clock.
TDI
Input
Boundary Scan Data Input.
TDO
Output
Boundary Scan Data Output.
TMS
Input
Boundary Scan Mode Select.
PWRDWN_B
Input
Active Low power-down pin (unsupported). Driving this pin Low can adversely affect
(unsupported) device operation and configuration. PWRDWN_B is internally pulled High, which is its
default state. It does not require an external pull-up.
Other Pins
DXN, DXP
N/A
Temperature-sensing diode pins (Anode: DXP, Cathode: DXN).
V_BATT
Input
Decryptor key memory backup supply. Connect V_BATT to V_CCAUX or GND if battery is
not used.
RSVD
N/A
Reserved pin - do not connect.
V_CCO
V_CCAUX
V_CCINT
GND
Input
Input
Input
Input
Power-supply pins for the output drivers (per bank).
Power-supply pins for auxiliary circuits.
Power-supply pins for the internal core logic.
Ground.
Notes:
1. All dedicated pins (JTAG and configuration) are powered by V_CCAUX (independent of the bank V_CCO voltage).
DS031-4 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 4 of 4
4