DS031 Datasheet, PDF (83/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
DCM Timing Parameters
All devices are 100% functionally tested. Because of the dif-
ficulty in directly measuring many internal timing parame-
ters, those parameters are derived from benchmark timing
patterns. The following guidelines reflect worst-case values
across the recommended operating conditions. All output
jitter and phase specifications are determined through sta-
tistical measurement at the package pins.
Operating Frequency Ranges
e
Table 38: Operating Frequency Ranges
Description
Symbol
Constraint
Speed Grade
Unit
s
-6
-5
-4
s
Output Clocks (Low Frequency Mode)
CLK0, CLK90, CLK180, CLK270
CLKOUT_FREQ_1X_LF_Min
24.00
24.00
24.00 MHz
CLKOUT_FREQ_1X_LF_Max
230.00
210.00
180.00 MHz
CLK2X, CLK2X180
CLKOUT_FREQ_2X_LF_Min
48.00
48.00
48.00 MHz
CLKOUT_FREQ_2X_LF_Max
450.00
420.00
360.00 MHz
CLKDV
CLKOUT_FREQ_DV_LF_Min
1.50
1.50
1.50 MHz
CLKOUT_FREQ_DV_LF_Max
150.00
140.00
120.00 MHz
CLKFX, CLKFX180
CLKOUT_FREQ_FX_LF_Min
24.00
24.00
24.00 MHz
CLKOUT_FREQ_FX_LF_Max
260.00
240.00
210.00 MHz
Input Clocks (Low Frequency Mode)
CLKIN (using DLL outputs) ^(1,3,4)
CLKIN_FREQ_DLL_LF_Min
24.00
24.00
24.00 MHz
CLKIN_FREQ_DLL_LF_Max
CLKIN (using CLKFX outputs) ^(2,3,4) CLKIN_FREQ_FX_LF_Min
230.00
1.00
210.00
1.00
180.00 MHz
1.00 MHz
CLKIN_FREQ_FX_LF_Max
260.00
240.00
210.00 MHz
PSCLK
PSCLK_FREQ_LF_Min
0.01
0.01
0.01 MHz
PSCLK_FREQ_LF_Max
450.00
420.00
360.00 MHz
Output Clocks (High Frequency Mode)
CLK0, CLK180
CLKOUT_FREQ_1X_HF_Min
48.00
48.00
48.00 MHz
CLKOUT_FREQ_1X_HF_Max
450.00
420.00
360.00 MHz
CLKDV
CLKOUT_FREQ_DV_HF_Min
3.00
3.00
3.00 MHz
CLKOUT_FREQ_DV_HF_Max
300.00
280.00
240.00 MHz
CLKFX, CLKFX180
CLKOUT_FREQ_FX_HF_Min
210.00
210.00
210.00 MHz
CLKOUT_FREQ_FX_HF_Max
350.00
320.00
270.00 MHz
Input Clocks (High Frequency Mode)
CLKIN (using DLL outputs) ^(1,3,4)
CLKIN_FREQ_DLL_HF_Min
48.00
48.00
48.00 MHz
CLKIN_FREQ_DLL_HF_Max
CLKIN (using CLKFX outputs) ^(2,3,4) CLKIN_FRQ_FX_HF_Min
450.00
50.00
420.00
50.00
360.00 MHz
50.00 MHz
CLKIN_FRQ_FX_HF_Max
350.00
320.00
270.00 MHz
PSCLK
PSCLK_FREQ_HF_Min
0.01
0.01
0.01 MHz
PSCLK_FREQ_HF_Max
450.00
420.00
360.00 MHz
Notes:
1. “DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. If both DLL and CLKFX outputs are used, follow the more restrictive specification.
3. If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used, then double these values.
4. If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used and CLKIN frequency > 400 MHz, CLKIN duty cycle must be within ±5% (45/55 to 55/45).
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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