DS031 Datasheet, PDF (31/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: Functional Description
Each block SelectRAM cell is a fully synchronous memory,
as illustrated in Figure 30. The two ports have independent
inputs and outputs and are independently clocked.
18 Kbit Block SelectRAM
DIA
DIPA
ADDRA
WEA
ENA
SSRA
CLKA
DOA
DOPA
DIB
DIPB
ADDRB
WEB
ENB
SSRB
CLKB
DOB
DOPB
DS031_11_071602
Figure 30: 18 Kbit Block SelectRAM in Dual-Port Mode
Port Aspect Ratios
Table 16 shows the depth and the width aspect ratios for the
18 Kbit block SelectRAM. Virtex-II block SelectRAM also
includes dedicated routing resources to provide an efficient
interface with CLBs, block SelectRAM, and multipliers.
Table 16: 18 Kbit Block SelectRAM Port Aspect Ratio
Width Depth Address Bus Data Bus Parity Bus
1
16,384 ADDR[13:0]
DATA[0]
N/A
2
8,192 ADDR[12:0] DATA[1:0]
N/A
4
4,096 ADDR[11:0] DATA[3:0]
N/A
9
2,048 ADDR[10:0] DATA[7:0] Parity[0]
18
1,024
ADDR[9:0] DATA[15:0] Parity[1:0]
36
512
ADDR[8:0] DATA[31:0] Parity[3:0]
falling clock edge causes the data to be loaded into the
memory cell addressed.
A write operation performs a simultaneous read operation.
Three different options are available, selected by configura-
tion:
1. “WRITE_FIRST”
The “WRITE_FIRST” option is a transparent mode. The
same clock edge that writes the data input (DI) into the
memory also transfers DI into the output registers DO
as shown in Figure 31.
Data_in
Internal
DI _Memory
DO
Data_out = Data_in
CLK
WE
Data_in
New
Address
aa
RAM Contents
Old
New
Data_out
New
DS031_14_102000
Figure 31: WRITE_FIRST Mode
2. “READ_FIRST”
The “READ_FIRST” option is a read-before-write mode.
The same clock edge that writes data input (DI) into the
memory also transfers the prior content of the memory
cell addressed into the data output registers DO, as
shown in Figure 32.
Data_in
Internal
DI _Memory
DO
Prior stored data
Read/Write Operations
The Virtex-II block SelectRAM read operation is fully syn-
chronous. An address is presented, and the read operation
is enabled by control signals WEA and WEB in addition to
ENA or ENB. Then, depending on clock polarity, a rising or
falling clock edge causes the stored data to be loaded into
output registers.
The write operation is also fully synchronous. Data and
address are presented, and the write operation is enabled
by control signals WEA or WEB in addition to ENA or ENB.
Then, again depending on the clock input mode, a rising or
CLK
WE
Data_in
New
Address
aa
RAM Contents
Old
New
Data_out
Old
DS031_13_102000
Figure 32: READ_FIRST Mode
DS031-2 (v3.5) November 5, 2007
Product Specification
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