DS031 Datasheet, PDF (64/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 17: IOB Output Switching Characteristics Standard Adjustments (Continued)
Description
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
HSTL, Class IV, 1.8V
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
SSTL, Class I, 2.5V
SSTL, Class II, 2.5V
SSTL, Class I, 3.3V
SSTL, Class II, 3.3V
AGP-2X/AGP (Accelerated Graphics Port)
LVDCI (Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI, 2.5V
LVDCI, 1.8V
LVDCI, 1.5V
LVDCI, 3.3V, Half-Impedance
LVDCI, 2.5V, Half-Impedance
LVDCI, 1.8V, Half-Impedance
LVDCI, 1.5V, Half-Impedance
HSLVDCI (High-Speed Low-Voltage DCI), 1.5V
HSLVDCI, 1.8V
HSLVDCI, 2.5V
HSLVDCI, 3.3V
GTL (Gunning Transceiver Logic) with DCI
GTL Plus with DCI
HSTL (High-Speed Transceiver Logic), Class I, with DCI
HSTL, Class II, with DCI
HSTL, Class III, with DCI
HSTL, Class IV, with DCI
HSTL, Class I, 1.8V, with DCI
HSTL, Class II, 1.8V, with DCI
HSTL, Class III, 1.8V, with DCI
HSTL, Class IV, 1.8V, with DCI
SSTL (Stub Series Terminated Logic), Class I, 1.8V, with DCI
SSTL, Class II, 1.8V, with DCI
SSTL, Class I, 2.5V, with DCI
SSTL, Class II, 2.5V, with DCI
SSTL, Class I, 3.3V, with DCI
SSTL, Class II, 3.3V, with DCI
IOSTANDARD
Attribute
HSTL_II_18
HSTL_III_18
HSTL_IV_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
AGP
LVDCI_33
LVDCI_25
LVDCI_18
LVDCI_15
LVDCI_DV2_33
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
GTL_DCI
GTLP_DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
SSTL18_I_DCI
SSTL18_II_DCI
SSTL2_I_DCI
SSTL2_II_DCI
SSTL3_I_DCI
SSTL3_II_DCI
Timing
Parameter
T_{OHSTL_II_18}
T_{OHSTL_III_18}
T_{OHSTL_IV_18}
T_{OSSTL18_I}
T_{OSSTL18_II}
T_{OSSTL2_I}
T_{OSSTL2_II}
T_{OSSTL3_I}
T_{OSSTL3_II}
T_OAGP
T_{OLVDCI_33}
T_{OLVDCI_25}
T_{OLVDCI_18}
T_{OLVDCI_15}
T_{OLVDCI_DV2_33}
T_{OLVDCI_DV2_25}
T_{OLVDCI_DV2_18}
T_{OLVDCI_DV2_15}
T_{OHSLVDCI_15}
T_{OHSLVDCI_18}
T_{OHSLVDCI_25}
T_{OHSLVDCI_33}
T_{OGTL_DCI}
T_{OGTLP_DCI}
T_{OHSTL_I_DCI}
T_{OHSTL_II_DCI}
T_{OHSTL_III_DCI}
T_{OHSTL_IV_DCI}
T_{OHSTL_I_DCI_18}
T_{OHSTL_II_DCI_18}
T_{OHSTL_III_DCI_18}
T_{OHSTL_IV_DCI_18}
T_{OSSTL18_I_DCI}
T_{OSSTL18_II_DCI}
T_{OSSTL2_I_DCI}
T_{OSSTL2_II_DCI}
T_{OSSTL3_I_DCI}
T_{OSSTL3_II_DCI}
Speed Grade
-6
-5
-4
–0.17 –0.18 –0.20
–0.16 –0.16 –0.18
–0.39 –0.40 –0.44
0.20 0.20 0.22
–0.05 –0.05 –0.06
0.21 0.22 0.24
–0.15 –0.16 –0.18
0.29 0.30 0.33
–0.05 –0.05 –0.05
–0.27 –0.28 –0.31
0.74 0.77 0.84
0.78 0.80 0.88
0.84 0.87 0.95
1.82 1.88 2.06
0.12 0.12 0.13
0.03 0.03 0.03
0.42 0.43 0.48
1.20 1.23 1.36
1.82 1.88 2.06
1.05 1.08 1.24
0.78 0.80 0.88
0.74 0.77 0.84
–0.31 –0.32 –0.35
–0.15 –0.16 –0.17
0.23 0.23 0.26
0.06 0.06 0.07
–0.17 –0.18 –0.20
–0.46 –0.47 –0.52
0.05 0.05 0.06
–0.03 –0.03 –0.03
–0.14 –0.14 –0.16
–0.41 –0.42 –0.47
0.36 0.37 0.40
0.06 0.06 0.07
0.12 0.13 0.14
–0.10 –0.10 –0.11
0.15 0.16 0.17
0.08 0.08 0.09
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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