DS031 Datasheet, PDF (10/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: Functional Description
Table 2: Supported Differential Signal I/O Standards
I/O Standard
LVPECL_33
Output
V_CCO
3.3
Input
V_CCO
N/R ⁽¹⁾
Input
V_REF
N/R
Output
V_OD
0.490 - 1.220
LDT_25
2.5
N/R
N/R 0.500 - 0.700
LVDS_33
3.3
N/R
N/R 0.250 - 0.400
LVDS_25
2.5
N/R
N/R 0.250 - 0.400
LVDSEXT_33
3.3
N/R
N/R 0.440 - 0.820
LVDSEXT_25
2.5
N/R
N/R 0.440 - 0.820
BLVDS_25
2.5
N/R
N/R 0.250 - 0.450
ULVDS_25
2.5
N/R
N/R 0.500 - 0.700
Notes:
1. N/R = no requirement.
Table 3: Supported DCI I/O Standards
I/O
Standard
LVDCI_33 ⁽¹⁾
LVDCI_DV2_33 ⁽¹⁾
LVDCI_25 ⁽¹⁾
LVDCI_DV2_25 ⁽¹⁾
LVDCI_18 ⁽¹⁾
LVDCI_DV2_18 ⁽¹⁾
LVDCI_15 ⁽¹⁾
LVDCI_DV2_15 ⁽¹⁾
Output
V_CCO
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
Input
V_CCO
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
Input
V_REF
N/R ⁽⁴⁾
N/R
N/R
N/R
N/R
N/R
N/R
N/R
Termination
Type
Series
Series
Series
Series
Series
Series
Series
Series
GTL_DCI
1.2
1.2
0.8
Single
GTLP_DCI
1.5
1.5
1.0
Single
HSTL_I_DCI
1.5
1.5
0.75
Split
HSTL_II_DCI
1.5
1.5
0.75
Split
HSTL_III_DCI
1.5
1.5
0.9
Single
HSTL_IV_DCI
1.5
1.5
0.9
Single
HSTL_I_DCI_18
1.8
1.8
0.9
Split
HSTL_II_DCI_18
1.8
1.8
0.9
Split
HSTL_III_DCI_18
1.8
1.8
1.1
Single
HSTL_IV_DCI_18
SSTL18_I_DCI ⁽³⁾
1.8
1.8
1.1
1.8
1.8
0.9
Single
Split
SSTL18_II_DCI
SSTL2_I_DCI ⁽²⁾
SSTL2_II_DCI⁽²⁾
SSTL3_I_DCI ⁽²⁾
SSTL3_II_DCI ⁽²⁾
1.8
1.8
0.9
Split
2.5
2.5
1.25
Split
2.5
2.5
1.25
Split
3.3
3.3
1.5
Split
3.3
3.3
1.5
Split
LVDS_25_DCI
2.5
2.5
N/R
Split
LVDSEXT_25_DCI
2.5
2.5
N/R
Split
Notes:
1. LVDCI_XX and LVDCI_DV2_XX are LVCMOS controlled
impedance buffers, matching the reference resistors or half of
the reference resistors.
2. These are SSTL compatible.
3. SSTL18_I is not a JEDEC-supported standard.
4. N/R = no requirement.
Logic Resources
IOB blocks include six storage elements, as shown in
Figure 2.
IOB
Reg
OCK1
DDR mux
Reg
OCK2
3-State
Reg
OCK1
DDR mux
Reg
OCK2
Output
Input
Reg
ICK1
Reg
ICK2
PAD
DS031_29_100900
Figure 2: Virtex-II IOB Block
Each storage element can be configured either as an
edge-triggered D-type flip-flop or as a level-sensitive latch.
On the input, output, and 3-state path, one or two DDR reg-
isters can be used.
Double data rate is directly accomplished by the two regis-
ters on each path, clocked by the rising edges (or falling
edges) from two different clock nets. The two clock signals
are generated by the DCM and must be 180 degrees out of
phase, as shown in Figure 3. There are two input, output,
and 3-state data signals, each being alternately clocked out.
DS031-2 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
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