DS031 Datasheet, PDF (52/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 5: Minimum Power On Current Required for Virtex-II Devices
Device (mA)
XC2V40, XC2V80,
XC2V250, XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000
I_CCINTMIN
200
250
350
400
500
650
800
1100
I_CCAUXMIN
100
100
100
100
100
100
100
100
I_CCOMIN
50
50
100
100
100
100
100
100
Notes:
1. Values specified for power on current parameters are Commercial Grade. For Industrial Grade values, multiply Commercial Grade
values by 1.25.
2. I_CCOMIN values listed here apply to the entire device (all banks).
General Power Supply Requirements
Proper decoupling of all FPGA power supplies is sessential.
Consult Xilinx Application Note XAPP623 for detailed infor-
mation on power distribution system design.
V_CCAUX powers critical resources in the FPGA. Thus,
V_CCAUX is especially susceptible to power supply noise.
Changes in V_CCAUX voltage outside of 200 mV peak to peak
should take place at a rate no faster than 10 mV per milli-
second. Techniques to help reduce jitter and period distor-
tion are provided in Xilinx Answer Record 13756, available
at www.support.xilinx.com.
V_CCAUX can share a power plane with 3.3V V_CCO, but only if
V_CCO does not have excessive noise. Using simultaneously
switching output (SSO) limits are essential for keeping
power supply noise to a minimum. Refer to XAPP689, “Man-
aging Ground Bounce in Large FPGAs,” to determine the
number of simultaneously switching outputs allowed per
bank at the package level.
DC Input and Output Levels
Values for V_IL and V_IH are recommended input voltages.
Values for I_OL and I_OH are guaranteed over the recom-
mended operating conditions at the V_OL and V_OH test
points. Only selected standards are tested. These are cho-
sen to ensure that all standards meet their specifications.
The selected standards are tested at minimum V_CCO with
the respective V_OL and V_OH voltage levels shown. Other
standards are sample tested.
Table 6: DC Input and Output Levels
Input/Output
Standard
V_IL
V, Min V, Max
LVTTL⁽¹⁾
– 0.5
0.8
LVCMOS33
– 0.5
0.8
LVCMOS25
– 0.5
0.7
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
PCI–X
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
35% V_CCO
35% V_CCO
30% V_CCO
30% V_CCO
Note 2
GTLP
GTL
HSTL I
HSTL II
HSTL III
HSTL IV
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
V_REF – 0.1
V_REF – 0.05
V_REF – 0.1
V_REF – 0.1
V_REF – 0.1
V_REF – 0.1
V_IH
V, Min
V, Max
2.0
3.6
2.0
3.6
1.7
2.7
65% V_CCO
65% V_CCO
50% V_CCO
50% V_CCO
Note 2
1.95
1.7
V_CCO + 0.5
V_CCO + 0.5
Note 2
V_REF + 0.1
V_REF + 0.05
V_REF + 0.1
V_REF + 0.1
V_REF + 0.1
V_REF + 0.1
V_CCO + 0.5
V_CCO + 0.5
V_CCO + 0.5
V_CCO + 0.5
V_CCO + 0.5
V_CCO + 0.5
V_OL
V, Max
0.4
0.4
0.4
0.4
0.4
10% V_CCO
10% V_CCO
Note 2
0.6
0.4
0.4
0.4
0.4
0.4
V_OH
V, Min
2.4
V_CCO – 0.4
V_CCO – 0.4
V_CCO – 0.4
V_CCO – 0.4
90% V_CCO
90% V_CCO
Note 2
n/a
n/a
V_CCO – 0.4
V_CCO – 0.4
V_CCO – 0.4
V_CCO – 0.4
I_OL
mA
24
24
24
16
16
Note 2
Note 2
Note 2
36
40
8
16
24
48
I_OH
mA
– 24
– 24
– 24
– 16
– 16
Note 2
Note 2
Note 2
n/a
n/a
–8
– 16
–8
–8
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
4