DS031 Datasheet, PDF (66/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4" of FR4
microstrip trace. Standard termination was used for all test-
ing. (See Virtex-II Platform FPGA User Guide for details.)
The propagation delay of the 4" trace is characterized sep-
arately and subtracted from the final measurement, and is
therefore not included in the generalized test setup shown in
Figure 1.
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it. (IBIS
models can be found on the web at http://support.xil-
inx.com/support/sw_ibis.htm.) Parameters V_REF, R_REF,
C_REF, and V_MEAS fully describe the test conditions for each
I/O standard. The most accurate prediction of propagation
delay in any given application can be obtained through IBIS
simulation, using the following method:
1. Simulate the output driver of choice into the generalized
test setup, using values from Table 19.
2. Record the time to V_MEAS.
3. Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
4. Record the time to V_MEAS.
5. Compare the results of steps 2 and 4. The increase or
decrease in delay should be added to or subtracted
from the I/O Output Standard Adjustment value
(Table 17) to yield the actual worst-case propagation
delay (clock-to-input) of the PCB trace.
V_REF
FPGA Output
R_REF
V_MEAS
(voltage level at which
delay measurement is taken)
C_REF
(probe capacitance)
ds083-3_06a_092503
Figure 1: Generalized Test Setup
Table 19: Output Delay Measurement Methodology
Description
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS ), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL, Class III
HSTL, Class IV
HSTL, Class I, 1.8V
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
HSTL, Class IV, 1.8V
IOSTANDARD
Attribute
LVTTL (all)
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3 (rising edge)
PCI33_3 (falling edge)
PCI66_3 (rising edge)
PCI66_3 (falling edge)
PCIX (rising edge)
PCIX (falling edge
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
HSTL_I_18
HSTL_II_18
HSTL_III_18
HSTL_IV_18
R_REF
(Ω)
1M
1M
1M
1M
1M
25
25
25
25
25
25
25
25
50
25
50
25
50
25
50
25
C_REF⁽¹⁾
( pF )
0
0
0
0
0
10 ⁽²⁾
10 ⁽²⁾
10 ⁽²⁾
10 ⁽²⁾
10 ⁽³⁾
10 ⁽³⁾
0
0
0
0
0
0
0
0
0
0
V_MEAS
(V)
1.4
1.65
1.25
0.9
0.75
0.94
2.03
0.94
2.03
0.94
2.03
0.8
1.0
V_REF
V_REF
0.9
0.9
V_REF
V_REF
1.1
1.1
V_REF
(V)
0
0
0
0
0
0
3.3
0
3.3
3.3
1.2
1.5
0.75
0.75
1.5
1.5
0.9
0.9
1.8
1.8
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
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