DS031 Datasheet, PDF (17/318 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Platform FPGAs: Functional Description
Table 8: SelectI/O-Ultra Differential Buffers With On-Chip Termination
IOSTANDARD Attribute
I/O Standard Description
External Termination
On-Chip Termination
LVDS 2.5V
LVDS_25
LVDS_25_DCI
LVDS Extended 2.5V
LVDSEXT_25
LVDSEXT_25_DCI
Figure 11 provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, and HSTL_IV_DCI I/O
standards. For a complete list, see the Virtex-II Platform FPGA User Guide.
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
Conventional
VCCO/2
R
Z0
VCCO/2 VCCO/2
R
R
Z0
VCCO
R
Z0
VCCO
VCCO
R
R
Z0
DCI Transmit
Conventional
Receive
Virtex-II DCI
VCCO/2
R
Z0
VCCO
2R
2R
Virtex-II DCI
VCCO/2
R
Z0
Virtex-II DCI
VCCO
R
Z0
VCCO
R
Virtex-II DCI
VCCO
R
Z0
Conventional
Transmit
DCI Receive
VCCO
2R
Z0
2R
Virtex-II DCI
VCCO/2
R
Z0
VCCO
2R
2R
Virtex-II DCI
VCCO
R
Z0
Virtex-II DCI
VCCO
R
Z0
VCCO
R
Virtex-II DCI
DCI Transmit
DCI Receive
Virtex-II DCI
VCCO
2R
Z0
2R
VCCO
2R
2R
Virtex-II DCI Virtex-II DCI
VCCO
2R
Z0
2R
Virtex-II DCI Virtex-II DCI
VCCO
R
Z0
Virtex-II DCI
VCCO
VCCO
R
R
Z0
Virtex-II DCI
Virtex-II DCI
VCCO
VCCO
2R
2R
Bidirectional
N/A
Z0
2R
2R
N/A
Reference
Resistor
VRN = VRP = R = Z0
Virtex-II DCI
Virtex-II DCI
VRN = VRP = R = Z0
VRN = VRP = R = Z0
Recommended
Z0⁽¹⁾
50 Ω
50 Ω
Note:
1. Z0 is the recommended PCB trace impedance.
50 Ω
Figure 11: HSTL DCI Usage Examples
VCCO
R
VCCO
R
Z0
Virtex-II DCI
Virtex-II DCI
VRN = VRP = R = Z0
50 Ω
DS031_65a_100201
DS031-2 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 2 of 4
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