DS031 Datasheet, PDF (97/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: Pinout Information
CS144/CSG144 Chip-Scale BGA
Package
As shown in Table 5, XC2V40, XC2V80, and XC2V250 Virtex-II devices are available in the CS144/CSG144 package. Pins
in the XC2V40, XC2V80, and XC2V250 devices are the same except for pin differences in the XC2V40 device, shown in the
No Connect column. Following this table are the CS144/CSG144 Chip-Scale BGA Package Specifications (0.80mm pitch).
Table 5: CS144/CSG144 — XC2V40, XC2V80, and XC2V250
Bank
Pin Description
Pin Number
No Connect in the XC2V40
0
IO_L01N_0
B3
0
IO_L01P_0
A3
0
IO_L02N_0
C4
0
IO_L02P_0
B4
0
IO_L03N_0/VRP_0
A4
0
IO_L03P_0/VRN_0
D5
0
IO_L94N_0/VREF_0
A5
0
IO_L94P_0
D6
0
IO_L95N_0/GCLK7P
C6
0
IO_L95P_0/GCLK6S
B6
0
IO_L96N_0/GCLK5P
A6
0
IO_L96P_0/GCLK4S
D7
1
IO_L96N_1/GCLK3P
A7
1
IO_L96P_1/GCLK2S
B7
1
IO_L95N_1/GCLK1P
A8
1
IO_L95P_1/GCLK0S
B8
1
IO_L94N_1
C8
1
IO_L94P_1/VREF_1
D8
1
IO_L03N_1/VRP_1
C9
1
IO_L03P_1/VRN_1
D9
1
IO_L02N_1
A10
1
IO_L02P_1
B10
1
IO_L01N_1
C10
1
IO_L01P_1
D10
2
IO_L01N_2
C13
2
IO_L01P_2
D11
2
IO_L02N_2/VRP_2
D12
2
IO_L02P_2/VRN_2
D13
2
IO_L03N_2
E10
2
IO_L03P_2/VREF_2
E11
2
IO_L93N_2
E13
NC
2
IO_L93P_2/VREF_2
F11
NC
2
IO_L94N_2
F12
2
IO_L94P_2
G10
DS031-4 (v3.5) November 5, 2007
Product Specification
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