DS031 Datasheet, PDF (91/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Date
08/01/03
10/14/03
03/29/04
06/24/04
03/01/05
Version
3.0
3.1
3.2
3.3
3.4
Revision
• Table 13: All Virtex-II devices and speed grades now Production.
• Updated values in Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables, based on values extracted from speedsfile version 1.116.
• Table 34 and Table 35: Revised test setup footnote to refer to Figure 1. Previously
specified a capacitive load parameter.
• Figure 1: Added note to figure regarding termination resistors.
• Table 1: Changed T_J description from “Operating junction temperature” to “Maximum
junction temperature”.
• In section General Power Supply Requirements, replaced reference to Answer Record
11713 with reference to XAPP689 regarding handling of simultaneously switching
outputs (SSO).
• In section I/O Standard Adjustment Measurement Methodology:
- Table 18 renamed Input Delay Measurement Methodology. Added footnotes.
- Added new Table 19, Output Delay Measurement Methodology.
- Replaced Figure 1, Generalized Test Setup, with new drawing.
- Revised and extended text describing output delay measurement procedure.
• Table 45, Table 47, and Table 48: All Source-Synchronous parameters for all devices
now available in these tables.
• XC2V8000 is no longer offered in the -6 speed grade. The following tables containing
parameters or other references to this device/grade combination were corrected
accordingly: Table 13, Table 14, Table 34, Table 35, Table 36, Table 37, Table 45,
Table 47, and Table 48.
• Table 39: For Input Clock Low/High Pulse Width, PSCLK and CLKIN, changed existing
Footnote (2) to new Footnote (3).
• Table 4:
- For XC2V40, added Maximum quiescent supply current specifications.
- For all devices, updated Typical specifications for I_CCINTQ and I_CCAUXQ.
• Section Power-On Power Supply Requirements, page 3: Added Footnote (1) qualifying
statement that power supplies can be turned on in any sequence.
• Added section Configuration Timing, page 27. This section includes new timing
diagrams as well as parameter specification tables formerly included in the Virtex-II
Platform FPGA User Guide.
• Table 20, Clock Distribution Switching Characteristics: Added parameter T_GSI/T_GIS
(Global Clock Buffer S Input Setup/Hold to I1 and I2 Inputs).
• Table 38, Operating Frequency Ranges: Added Footnote (4) to all four CLKIN
parameters.
• Recompiled for backward compatibility with Acrobat 4 and above.
• Table 1: Added T_SOL parameters for Pb-free package devices.
• Updated values in Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables, based on values extracted from speedsfile version 1.120.
• Table 2: Corrected Footnote (1) to require connecting V_BATT to V_CCAUX or GND if
battery is not used.
• Table 3: Corrected "V_REF current per bank" to "V_REF current per pin."
• Section Power-On Power Supply Requirements: Added word “monotonically” to
description of supply voltage ramp-on requirements. Added sentence to footnote (1)
indicating that if the stated requirements are violated, no damage to the device will
result, but configuration will probably fail.
• Figure 3 and Figure 4: Corrected to show DOUT transitions driven by falling edge of
CCLK.
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
43