DS031 Datasheet, PDF (79/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Virtex-II Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, With DCM
Table 34: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, With DCM
Speed Grade
Description
Symbol
Device
-6
-5
-4
Units
LVTTL Global Clock Input to Output delay using
Output flip-flop, 12 mA, Fast Slew Rate, with
DCM.
For data output with different standards, adjust
the delays with the values shown in IOB Output
Switching Characteristics Standard
Adjustments, page 14.
Global Clock and OFF with DCM
T_ICKOFDCM
XC2V40
1.10
1.28
XC2V80
1.10
1.28
1.48
ns
1.48
ns
XC2V250
1.10
1.28
1.48
ns
XC2V500
1.10
1.28
1.48
ns
XC2V1000
1.10
1.28
1.48
ns
XC2V1500
1.10
1.28
1.48
ns
XC2V2000
1.10
1.28
1.48
ns
XC2V3000
1.19
1.38
1.59
ns
XC2V4000
1.19
1.38
1.59
ns
XC2V6000
1.64
1.88
2.17
ns
XC2V8000
1.88
2.17
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 50% V_CC threshold with test setup shown in Figure 1. For other I/O standards, see Table 19.
DS031-3 (v3.5) November 5, 2007
Product Specification
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