DS031 Datasheet, PDF (88/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 47: Sample Window
Speed Grade
Description
Symbol
Device
-6
-5
-4
Units
Sampling Error at Receiver Pins⁽¹⁾
T_SAMP
XC2V40
500
500
550
ps
XC2V80
500
500
550
ps
XC2V250
500
500
550
ps
XC2V500
500
500
550
ps
XC2V1000
500
500
550
ps
XC2V1500
500
500
550
ps
XC2V2000
500
500
550
ps
XC2V3000
500
500
550
ps
XC2V4000
500
500
550
ps
XC2V6000
500
500
550
ps
XC2V8000
500
550
ps
Notes:
1. This parameter indicates the total sampling error of Virtex-II DDR input registers across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 and CLK180 DCM jitter
- Worst-case Duty-Cycle Distortion - T_{DCD_CLK180}
- DCM accuracy (phase offset)
- DCM phase shift resolution.
These measurements do not include package or clock tree skew.
Table 48: Pin-to-Pin Setup/Hold: Source-Synchronous Configuration
Speed Grade
Description
Symbol Device
-6
-5
-4
Data Input Set-Up and Hold Times Relative to a Forwarded
Clock Input Pin, Using DCM and Global Clock Buffer.
For situations where clock and data inputs conform to
different standards, adjust the setup and hold values
accordingly using the values shown in IOB Input Switching
Characteristics Standard Adjustments, page 11.
No Delay
Global Clock and IFF with DCM
T_PSDCM/
T_PHDCM
XC2V40
XC2V80
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
0.2/0.5
XC2V250 0.2/0.5
0.2/0.5
0.2/0.5
XC2V500 0.2/0.5
0.2/0.5
0.2/0.5
XC2V1000 0.2/0.5
0.2/0.5
0.2/0.5
XC2V1500 0.2/0.5
0.2/0.5
0.2/0.5
XC2V2000 0.2/0.5
0.2/0.5
0.2/0.5
XC2V3000 0.2/0.5
0.2/0.5
0.2/0.6
XC2V4000 0.2/0.5
0.2/0.6
0.2/0.6
XC2V6000 0.2/0.5
0.2/0.6
0.2/0.6
XC2V8000
0.2/0.6
0.2/0.7
Notes:
1. IFF = Input Flip-Flop
2. The timing values were measured using the fine-phase adjustment feature of the DCM.
3. The worst-case duty-cycle distortion and DCM jitter on CLK0 and CLK180 is included in these measurements.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
40