DS031 Datasheet, PDF (58/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 14: IOB Input Switching Characteristics (Continued)
Speed Grade
Description
Symbol
Device
-6
-5
-4
Propagation Delays
Pad to output IQ via transparent
latch, no delay
T_IOPLI
0.83
0.91
1.05
All
Pad to output IQ via transparent
T_IOPLID
XC2V40
3.23
3.55
4.09
latch, with delay
XC2V80
3.23
3.55
4.09
XC2V250
3.23
3.55
4.09
XC2V500
3.23
3.55
4.09
XC2V1000
3.23
3.55
4.09
XC2V1500
3.23
3.55
4.09
XC2V2000
3.23
3.55
4.09
XC2V3000
3.32
3.65
4.20
XC2V4000
3.32
3.65
4.20
XC2V6000
3.60
3.95
4.55
XC2V8000
3.95
4.55
Clock CLK to output IQ
T_IOCKIQ
All
Setup and Hold Times With Respect to Clock at IOB Input
Register
0.67
0.77
Pad, no delay
Pad, with delay
T_IOPICK/T_IOICKP
T_IOPICKD/T_IOICKPD
All
XC2V40
XC2V80
0.84/–0.36
3.24/–2.04
3.24/–2.04
0.92/–0.39
3.57/–2.24
3.57/–2.24
1.06/–0.45
4.10/–2.58
4.10/–2.58
XC2V250 3.24/–2.04 3.57/–2.24 4.10/–2.58
XC2V500 3.24/–2.04 3.57/–2.24 4.10/–2.58
XC2V1000 3.24/–2.04 3.57/–2.24 4.10/–2.58
XC2V1500 3.24/–2.04 3.57/–2.24 4.10/–2.58
XC2V2000 3.24/–2.04 3.57/–2.24 4.10/–2.58
XC2V3000 3.33/–2.10 3.67/–2.31 4.22/–2.66
XC2V4000 3.33/–2.10 3.67/–2.31 4.22/–2.66
XC2V6000 3.61/–2.29 3.97/–2.52 4.56/–2.90
XC2V8000
3.97/–2.52 4.56/–2.90
ICE input
SR input (IFF, synchronous)
Set/Reset Delays
T_IOICECK/T_IOCKICE
All
T_IOSRCKI
All
0.21/ 0.04 0.24/ 0.04
0.27
0.30
0.34
SR input to IQ (asynchronous)
T_IOSRIQ
All
1.11
1.22
1.40
GSR to output IQ
T_GSRQ
All
5.44
5.98
6.88
Notes:
1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 18.
Units
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Max
ns, Max
DS031-3 (v3.5) November 5, 2007
Product Specification
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