DS031 Datasheet, PDF (30/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: Functional Description
18 Kbit Block SelectRAM
DI
DIP
ADDR
WE
EN
SSR
CLK
DO
DOP
DS031_10_071602
Figure 29: 18 Kbit Block SelectRAM Memory in
Single-Port Mode
Dual-Port Configuration
As a dual-port RAM, each port of block SelectRAM has
access to a common 18 Kbit memory resource. These are
fully synchronous ports with independent control signals for
each port. The data widths of the two ports can be config-
ured independently, providing built-in bus-width conversion.
Table 15 illustrates the different configurations available on
ports A and B.
If both ports are configured in either 2K x 9-bit, 1K x 18-bit,
or 512 x 36-bit configurations, the 18 Kbit block is accessi-
ble from port A or B. If both ports are configured in either
16K x 1-bit, 8K x 2-bit. or 4K x 4-bit configurations, the
16 K-bit block is accessible from Port A or Port B. All other
configurations result in one port having access to an 18 Kbit
memory block and the other port having access to a 16 K-bit
subset of the memory block equal to 16 Kbits.
Table 15: Dual-Port Mode Configurations
Port A
16K x 1
16K x 1
Port B
16K x 1
8K x 2
Port A
8K x 2
8K x 2
Port B
8K x 2
4K x 4
Port A
4K x 4
4K x 4
Port B
4K x 4
2K x 9
Port A
2K x 9
2K x 9
Port B
2K x 9
1K x 18
Port A
1K x 18
1K x 18
Port B
1K x 18
512 x 36
Port A
512 x 36
Port B
512 x 36
16K x 1
4K x 4
8K x 2
2K x 9
4K x 4
1K x 18
2K x 9
512 x 36
16K x 1
2K x 9
8K x 2
1K x 18
4K x 4
512 x 36
16K x 1
1K x 18
8K x 2
512 x 36
16K x 1
512 x 36
DS031-2 (v3.5) November 5, 2007
Product Specification
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