DS031 Datasheet, PDF (12/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: Functional Description
(O/T) 1
(O/T) CE
(O/T) CLK1
Shared ^SR
by all
registers REV
(O/T) CLK2
(O/T) 2
FF
LATCH
D1 ^Q1
Attribute INIT1
INIT0
SRHIGH
SRLOW
CE
CK1
SR REV
FF1
DDR MUX
FF2
(OQ or TQ)
FF
LATCH
D2 Q2
CE
CK2
SR REV
Attribute _INIT1
INIT0
SRHIGH
SRLOW
Reset Type
SYNC
ASYNC
Figure 4: Register / Latch Configuration in an IOB Block
DS031_25_110300
VCCO
OBUF
Program
Current
Clamp
Diode
VCCO
Weak
Keeper
10KΩ –
60KΩ
VCCO
10KΩ –
60KΩ
PAD
Program
Delay
IBUF
VCCAUX = 3.3V
VCCINT = 1.5V
DS031_23_022205
Figure 5: LVTTL, LVCMOS or PCI SelectI/O-Ultra
Standards
Input/Output Individual Options
Each device pad has optional pull-up and pull-down in all
SelectI/O-Ultra configurations. Each device pad has
optional weak-keeper in LVTTL, LVCMOS, and PCI
SelectI/O-Ultra configurations, as illustrated in Figure 5.
Values of the optional pull-up and pull-down resistors are in
the range 10 - 60 KΩ, which is the specification for V_CCO
when operating at 3.3V (from 3.0 to 3.6V only). The clamp
diode is always present, even when power is not.
The optional weak-keeper circuit is connected to each user
I/O pad. When selected, the circuit monitors the voltage on
the pad and weakly drives the pin High or Low. If the pin is
connected to a multiple-source signal, the weak-keeper
holds the signal in its last state if all drivers are disabled.
Maintaining a valid logic level in this way eliminates bus
chatter. An enabled pull-up or pull-down overrides the
weak-keeper circuit.
LVTTL sinks and sources current up to 24 mA. The current
is programmable for LVTTL and LVCMOS SelectI/O-Ultra
standards (see Table 4). Drive-strength and slew-rate con-
trols for each output driver, minimize bus transients. For
LVDCI and LVDCI_DV2 standards, drive strength and
slew-rate controls are not available.
DS031-2 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
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