DS031 Datasheet, PDF (40/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: Functional Description
Routing
DCM Locations/Organization
Virtex-II DCMs are placed on the top and bottom of each
block RAM and multiplier column. The number of DCMs
depends on the device size, as shown in Table 24.
Table 24: DCM Organization
Device
Columns
DCMs
XC2V40
2
4
XC2V80
2
4
XC2V250
4
8
XC2V500
4
8
XC2V1000
4
8
XC2V1500
4
8
XC2V2000
4
8
XC2V3000
6
12
XC2V4000
6
12
XC2V6000
6
12
XC2V8000
6
12
Active Interconnect Technology
Local and global Virtex-II routing resources are optimized
for speed and timing predictability, as well as to facilitate IP
cores implementation. Virtex-II Active Interconnect Technol-
ogy is a fully buffered programmable routing matrix. All rout-
ing resources are segmented to offer the advantages of a
hierarchical solution. Virtex-II logic features like CLBs,
IOBs, block RAM, multipliers, and DCMs are all connected
to an identical switch matrix for access to global routing
resources, as shown in Figure 47.
Switch
Matrix
CLB
Switch
Matrix
Switch
Matrix
Switch
IOB
Matrix
18Kb
BRAM
MULT
18 x 18
Switch
Matrix
Switch
Matrix
DCM
Switch
Matrix
DS031_55_022205
Figure 47: Active Interconnect Technology
Each Virtex-II device can be represented as an array of
switch matrixes with logic blocks attached, as illustrated in
Figure 48.
Switch
Matrix
IOB
Switch
Matrix
IOB
Switch
Matrix
IOB
Switch
Matrix
DCM
Switch
Matrix
Switch
Matrix
IOB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
Switch
Matrix
Switch
Matrix
IOB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
Switch
Matrix
Switch
Matrix
IOB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
Switch
Matrix
Switch
Matrix
IOB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
Figure 48: Routing Resources
Switch
Matrix
DS031_34_022205
DS031-2 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
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