DS031 Datasheet, PDF (63/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 17: IOB Output Switching Characteristics Standard Adjustments (Continued)
Description
LVCMOS, 2.5V, Fast, 16 mA
LVCMOS, 2.5V, Fast, 24 mA
LVCMOS, 1.8V, Slow, 2 mA
LVCMOS, 1.8V, Slow, 4 mA
LVCMOS, 1.8V, Slow, 6 mA
LVCMOS, 1.8V, Slow, 8 mA
LVCMOS, 1.8V, Slow, 12 mA
LVCMOS, 1.8V, Slow, 16 mA
LVCMOS, 1.8V, Fast, 2 mA
LVCMOS, 1.8V, Fast, 4 mA
LVCMOS, 1.8V, Fast, 6 mA
LVCMOS, 1.8V, Fast, 8 mA
LVCMOS, 1.8V, Fast, 12 mA
LVCMOS, 1.8V, Fast, 16 mA
LVCMOS, 1.5V, Slow, 2 mA
LVCMOS, 1.5V, Slow, 4 mA
LVCMOS, 1.5V, Slow, 6 mA
LVCMOS, 1.5V, Slow, 8 mA
LVCMOS, 1.5V, Slow, 12 mA
LVCMOS, 1.5V, Slow, 16 mA
LVCMOS, 1.5V, Fast, 2 mA
LVCMOS, 1.5V, Fast, 4 mA
LVCMOS, 1.5V, Fast, 6 mA
LVCMOS, 1.5V, Fast, 8 mA
LVCMOS, 1.5V, Fast, 12 mA
LVCMOS, 1.5V, Fast, 16 mA
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDS, 3.3V
LVDSEXT (LVDS Extended Mode), 2.5V
LVDSEXT, 3.3V
ULVDS (Ultra LVDS), 2.5V
BLVDS (Bus LVDS), 2.5V
LDT (HyperTransport), 2.5V
LVPECL (Low-Voltage Positive Electron-Coupled Logic), 3.3V
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL, Class III
HSTL, Class IV
HSTL, Class I, 1.8V
IOSTANDARD
Attribute
LVCMOS25_F16
LVCMOS25_F24
LVCMOS18_S2
LVCMOS18_S4
LVCMOS18_S6
LVCMOS18_S8
LVCMOS18_S12
LVCMOS18_S16
LVCMOS18_F2
LVCMOS18_F4
LVCMOS18_F6
LVCMOS18_F8
LVCMOS18_F12
LVCMOS18_F16
LVCMOS15_S2
LVCMOS15_S4
LVCMOS15_S6
LVCMOS15_S8
LVCMOS15_S12
LVCMOS15_S16
LVCMOS15_F2
LVCMOS15_F4
LVCMOS15_F6
LVCMOS15_F8
LVCMOS15_F12
LVCMOS15_F16
LVDS_25
LVDS_33
LVDSEXT_25
LVDSEXT_33
ULVDS_25
BLVDS_25
LDT_25
LVPECL_33
PCI33_3
PCI66_3
PCIX
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
HSTL_I_18
Timing
Parameter
T_{OLVCMOS25_F16}
T_{OLVCMOS25_F24}
T_{OLVCMOS18_S2}
T_{OLVCMOS18_S4}
T_{OLVCMOS18_S6}
T_{OLVCMOS18_S8}
T_{OLVCMOS18_S12}
T_{OLVCMOS18_S16}
T_{OLVCMOS18_F2}
T_{OLVCMOS18_F4}
T_{OLVCMOS18_F6}
T_{OLVCMOS18_F8}
T_{OLVCMOS18_F12}
T_{OLVCMOS18_F16}
T_{OLVCMOS15_S2}
T_{OLVCMOS15_S4}
T_{OLVCMOS15_S6}
T_{OLVCMOS15_S8}
T_{OLVCMOS15_S12}
T_{OLVCMOS15_S16}
T_{OLVCMOS15_F2}
T_{OLVCMOS15_F4}
T_{OLVCMOS15_F6}
T_{OLVCMOS15_F8}
T_{OLVCMOS15_F12}
T_{OLVCMOS15_F16}
T_{OLVDS_25}
T_{OLVDS_33}
T_{OLVDSEXT_25}
T_{OLVDSEXT_33}
T_{OULVDS_25}
T_{OBLVDS_25}
T_{OLDT_25}
T_{OLVPECL_33}
T_{OPCI33_3}
T_{OPCI66_3}
T_OPCIX
T_OGTL
T_OGTLP
T_{OHSTL_I}
T_{OHSTL_II}
T_{OHSTL_III}
T_{OHSTL_IV}
T_{OHSTL_I_18}
Speed Grade
-6
-5
-4
–0.18 –0.19 –0.21
–0.35 –0.36 –0.40
15.62 16.10 17.71
10.20 10.51 11.57
7.52 7.75 8.53
6.87 7.08 7.78
5.54 5.71 6.28
5.31 5.47 6.02
5.55 5.72 6.30
1.89 1.95 2.15
0.83 0.85 0.94
0.70 0.72 0.80
0.26 0.27 0.30
0.23 0.23 0.26
18.96 19.55 21.50
12.77 13.17 14.48
12.05 12.42 13.66
9.75 10.06 11.06
9.04 9.32 10.25
8.21 8.46 9.31
5.09 5.25 5.78
2.01 2.07 2.27
1.46 1.51 1.66
0.93 0.96 1.05
0.74 0.77 0.84
0.67 0.69 0.75
–0.31 –0.32 –0.36
–0.25 –0.26 –0.29
–0.18 –0.19 –0.21
–0.17 –0.18 –0.19
–0.20 –0.21 –0.23
0.67 0.69 0.76
–0.20 –0.21 –0.23
0.29 0.30 0.33
1.15 1.19 1.31
–0.01 –0.01 –0.01
–0.01 –0.01 –0.01
–0.31 –0.32 –0.36
–0.17 –0.18 –0.20
0.26 0.27 0.29
–0.15 –0.16 –0.17
–0.17 –0.17 –0.19
–0.40 –0.41 –0.45
0.03 0.03 0.04
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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