DS031 Datasheet, PDF (100/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: Pinout Information
Table 5: CS144/CSG144 — XC2V40, XC2V80, and XC2V250
Bank
Pin Description
Pin Number
No Connect in the XC2V40
NA
CCLK
NA
PROG_B
NA
DONE
NA
M0
NA
M1
NA
M2
NA
TCK
NA
TDI
NA
TDO
NA
TMS
NA
PWRDWN_B
NA
HSWAP_EN
NA
RSVD
NA
RSVD
NA
VBATT
NA
RSVD
M13
B1
N12
N2
M2
M3
B12
C1
C11
A13
M12
A1
A2
B2
A12
B11
NA
VCCAUX
C2
NA
VCCAUX
N1
NA
VCCAUX
N13
NA
VCCAUX
B13
NA
VCCINT
H2
NA
VCCINT
L7
NA
VCCINT
H13
NA
VCCINT
C7
NA
GND
E1
NA
GND
G2
NA
GND
J1
NA
GND
J4
NA
GND
M5
NA
GND
L9
NA
GND
J11
NA
GND
H10
NA
GND
F13
NA
GND
E12
NA
GND
B9
NA
GND
C5
Notes:
1. See Table 4 for an explanation of the signals available on this pin.
DS031-4 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
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