DS031 Datasheet, PDF (57/318 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Platform FPGAs: DC and Switching Characteristics
Virtex-II Switching Characteristics
Switching characteristics in this document are specified on
a per-speed-grade basis and can be designated as
Advance, Preliminary, or Production. Note that Virtex-II Per-
formance Characteristics, page 7 are subject to these
guidelines as well. Each designation is defined as follows:
Advance: These speed files are based on simulations only
and are typically available soon after device design specifi-
cations are frozen. Although speed grades with this desig-
nation are considered relatively stable and conservative,
some under-reporting might still occur.
Preliminary: These speed files are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
Production: These speed files are released once enough
production silicon of a particular device family member has
been characterized to provide full correlation between
speed files and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ-
ically, the slowest speed grades transition to Production
before faster speed grades.
Since individual family members are produced at different
times, the migration from one category to another depends
completely on the status of the fabrication process for each
device. Table 13 correlates the current status of each
Virtex-II device with a corresponding speed grade designa-
tion.
All specifications are always representative of worst-case
supply voltage and junction temperature conditions.
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the Xilinx static timing analyzer
and back-annotate to the simulation net list. Unless other-
wise noted, values apply to all Virtex-II devices.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for
LVTTL levels. For other standards, adjust the delays with
the values shown in IOB Input Switching Characteristics
Standard Adjustments, page 11.
Table 13: Virtex-II Device Speed Grade Designations
Speed Grade Designations
Device
Advance Preliminary Production
XC2V40
-6, -5, -4
XC2V80
-6, -5, -4
XC2V250
-6, -5, -4
XC2V500
-6, -5, -4
XC2V1000
-6, -5, -4
XC2V1500
-6, -5, -4
XC2V2000
-6, -5, -4
XC2V3000
-6, -5, -4
XC2V4000
-6, -5, -4
XC2V6000
-6, -5, -4
XC2V8000
-5, -4
Table 14: IOB Input Switching Characteristics
Description
Propagation Delays
Pad to I output, no delay
Pad to I output, with delay
Symbol
T_IOPI
T_IOPID
Device
All
XC2V40
XC2V80
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
Speed Grade
-6
-5
-4
0.69
0.76
0.88
1.92
2.11
2.43
1.92
2.11
2.43
1.92
2.11
2.43
1.92
2.11
2.43
1.92
2.11
2.43
1.92
2.11
2.43
1.92
2.11
2.43
1.97
2.16
2.49
1.97
2.16
2.49
2.10
2.31
2.66
2.31
2.66
Units
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
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