DS031 Datasheet, PDF (75/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Configuration Timing
Configuration Memory Clearing Parameters
Power-up timing of configuration signals is shown in Figure 2; corresponding timing characteristics are listed in Table 30.
V_CC
PROG_B
INIT_B
CCLK
(Output
or Input)
M0, M1, M2*
(Required)
1 T_POR
2 ^TPL
3
T_ICCK
*Can be either 0 or 1, but must not toggle during and after configuration.
ds083-3_07_012004
Figure 2: Configuration Power-Up Timing
Table 30: Power-Up Timing Characteristics
Description
Figure
References
Symbol
Value
Units
Power-on reset
Program latency
CCLK (output) delay
1
T_POR
T_PL + 2
ms, max
2
T_PL
4
μs per frame, max
0.5
μs, min
3
T_ICCK
4.0
μs, max
Program pulse width
T_PROGRAM
300
ns, min
Notes:
1. The M2, M1, and M0 mode pins should be set at a constant DC voltage level, either through pull-up or pull-down resistors, or tied
directly to ground or V_CCAUX. The mode pins should not be toggled during and after configuration.
Master/Slave Serial Mode Parameters
Clock timing for Slave Serial configuration programming is shown in Figure 3, with Master Serial clock timing shown in
Figure 4. Programming parameters for both Slave and Master modes are given in Table 31.
DS031-3 (v3.5) November 5, 2007
Product Specification
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