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DS031 Datasheet, PDF (67/318 Pages) Xilinx, Inc – Summary of Features
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Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 19: Output Delay Measurement Methodology
Description
IOSTANDARD
Attribute
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL18_I
SSTL, Class II, 1.8V
SSTL18_II
SSTL, Class I, 2.5V
SSTL2_I
SSTL, Class II, 2.5V
SSTL2_II
SSTL, Class I, 3.3V
SSTL3_I
SSTL, Class II, 3.3V
SSTL3_II
AGP-2X/AGP (Accelerated Graphics Port)
AGP-2X/AGP (rising edge)
AGP-2X/AGP (falling edge)
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDS_25
LVDS, 3.3V
LVDSEXT_25
LVDSEXT (LVDS Extended Mode), 2.5V
LVDS_33
LVDSEXT, 3.3V
LVDSEXT_33
BLVDS (Bus LVDS), 2.5V
BLVDS_25
LDT (HyperTransport), 2.5V
LDT_25
LVPECL (Low-Voltage Positive Electron-Coupled Logic), 3.3V
LVPECL_33
LVDCI/HSLVDCI
(Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI_33, HSLVDCI_33
LVDCI/HSLVDCI, 2.5V
LVDCI_25, HSLVDCI_25
LVDCI/HSLVDCI, 1.8V
LVDCI_18, HSLVDCI_18
LVDCI/HSLVDCI, 1.5V
LVDCI_15, HSLVDCI_15
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI
HSTL_I_DCI, HSTL_II_DCI
HSTL, Class III & IV, with DCI
HSTL_III_DCI, HSTL_IV_DCI
HSTL, Class I & II, 1.8V, with DCI
HSTL_I_DCI_18, HSTL_II_DCI_18
HSTL, Class III & IV, 1.8V, with DCI
HSTL_III_DCI_18, HSTL_IV_DCI_18
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI
SSTL18_I_DCI, SSTL18_II_DCI
SSTL, Class I & II, 2.5V, with DCI
SSTL2_I_DCI, SSTL2_II_DCI
SSTL, Class I & II, 3.3V, with DCI
SSTL3_I_DCI, SSTL3_II_DCI
GTL (Gunning Transceiver Logic) with DCI
GTL_DCI
GTL Plus with DCI
GTLP_DCI
Notes:
1. CREF is the capacitance of the probe, nominally 0 pF.
2. Per PCI specifications.
3. Per PCI-X specifications.
RREF
(Ω)
50
25
50
25
50
25
50
50
50
50
50
50
1M
50
1M
1M
1M
1M
1M
50
50
50
50
50
50
50
50
50
CREF(1)
( pF )
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VMEAS
(V)
VREF
VREF
VREF
VREF
VREF
VREF
0.94
2.03
VREF
VREF
VREF
VREF
1.2
VREF
1.23
1.65
1.25
0.9
0.75
VREF
0.9
VREF
1.1
VREF
VREF
VREF
0.8
1.0
VREF
(V)
0.9
0.9
1.25
1.25
1.5
1.5
0
3.3
1.2
1.2
1.2
1.2
0
0.6
0
0
0
0
0
0.75
1.5
0.9
1.8
0.9
1.25
1.5
1.2
1.5
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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