DS031 Datasheet, PDF (36/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: Functional Description
Clock
Pad
I
Clock
Buffer
0
Clock Distribution
Clock
Pad
CLKIN
DCM
CLKOUT
I
Clock
Buffer
0
Clock Distribution
DS031_43_101000
Figure 39: Virtex-II Clock Distribution Configurations
Global clock buffers are used to distribute the clock to some
or all synchronous logic elements (such as registers in
CLBs and IOBs, and SelectRAM blocks.
Eight global clocks can be used in each quadrant of the
Virtex-II device. Designers should consider the clock distri-
bution detail of the device prior to pin-locking and floorplan-
ning (see the Virtex-II User Guide).
Figure 40 shows clock distribution in Virtex-II devices.
In each quadrant, up to eight clocks are organized in clock
rows. A clock row supports up to 16 CLB rows (eight up and
eight down). For the largest devices a new clock row is
added, as necessary.
To reduce power consumption, any unused clock branches
remain static.
Global clocks are driven by dedicated clock buffers (BUFG),
which can also be used to gate the clock (BUFGCE) or to mul-
tiplex between two independent clock inputs (BUFGMUX).
8 BUFGMUX
NW
NW ^{8 BUFGMUX} NE
8
NE
8
8 max
16 Clocks
16 Clocks
8
SW _{8 BUFGMUX} SE
SW
8
SE
8 BUFGMUX
Figure 40: Virtex-II Clock Distribution
DS031_45_120200
The most common configuration option of this element is as
a buffer. A BUFG function in this (global buffer) mode, is
shown in Figure 41.
BUFG
I
O
DS031_61_101200
Figure 41: Virtex-II BUFG Function
The Virtex-II global clock buffer BUFG can also be config-
ured as a clock enable/disable circuit (Figure 42), as well as
a two-input clock multiplexer (Figure 43). A functional
description of these two options is provided below. Each of
them can be used in either of two modes, selected by con-
figuration: rising clock edge or falling clock edge.
This section describes the rising clock edge option. For the
opposite option, falling clock edge, just change all "rising"
references to "falling" and all "High" references to "Low",
except for the description of the CE or S levels. The rising
clock edge option uses the BUFGCE and BUFGMUX prim-
itives. The falling clock edge option uses the BUFGCE_1
and BUFGMUX_1 primitives.
BUFGCE
If the CE input is active (High) prior to the incoming rising
clock edge, this Low-to-High-to-Low clock pulse passes
through the clock buffer. Any level change of CE during the
incoming clock High time has no effect.
DS031-2 (v3.5) November 5, 2007
Product Specification
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