DS031 Datasheet, PDF (94/318 Pages) Xilinx, Inc – Summary of Features

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Virtex-II Platform FPGAs: Pinout Information
Table 3: Virtex-II Device/Package Combinations and Maximum Number of Available I/Os
Available I/Os
XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V XC2V
Package 40
80
250
500 1000 1500 2000 3000 4000
CS144
88
92
92
-
-
-
-
-
-
FG256
88
120
172
172
172
-
-
-
-
FG456
-
-
200
264
324
-
-
-
-
FG676
-
-
-
-
-
392
456
484
-
FF896
-
-
-
-
432
528
624
-
-
FF1152
-
-
-
-
-
-
-
720
824
FF1517
-
-
-
-
-
-
-
-
912
BG575
-
-
-
-
328
392
408
-
-
BG728
-
-
-
-
-
-
-
516
-
BF957
-
-
-
-
-
-
624
684
684
XC2V
6000
-
-
-
-
-
824
1,104
-
-
684
XC2V
8000
-
-
-
-
-
824
1,108
-
-
-
Virtex-II Pin Definitions
This section describes the pinouts for Virtex-II devices in the
following packages:
• CS144: wire-bond chip-scale ball grid array (BGA) of
0.80 mm pitch
• FG256, FG456, and FG676: wire-bond fine-pitch BGA
of 1.00 mm pitch
• FF896, FF1152, FF1517: flip-chip fine-pitch BGA of
1.00 mm pitch
• BG575 and BG728: wire-bond BGA of 1.27 mm pitch
• BF957: flip-chip BGA of 1.27 mm pitch
All of the devices supported in a particular package are
pinout compatible and are listed in the same table (one
table per package). In addition, the FG456 and FG676
packages are compatible, as are the FF896 and FF1152
packages. Pins that are not available for the smallest
devices are listed in right-hand columns.
Each device is split into eight I/O banks to allow for flexibility
in the choice of I/O standards (see the Virtex-II Data Sheet).
Global pins, including JTAG, configuration, and
power/ground pins, are listed at the end of each table.
Table 4 provides definitions for all pin types.
The FG256 pinouts (Table 6) is included as an example. All
Virtex-II pinout tables are available on the distribution
CD-ROM, or on the web (at http://www.xilinx.com).
DS031-4 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 4 of 4
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