DS031 Datasheet, PDF (103/318 Pages) Xilinx, Inc – Summary of Features

R
Virtex-II Platform FPGAs: Pinout Information
Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank
Pin Description
Pin Number No Connect in XC2V40
1
IO_L92P_1
E11
NC
1
IO_L05N_1
A11
NC
1
IO_L05P_1
B11
NC
1
IO_L04N_1
C11
NC
1
IO_L04P_1/VREF_1
D11
NC
1
IO_L03N_1/VRP_1
A12
1
IO_L03P_1/VRN_1
B12
1
IO_L02N_1
C12
1
IO_L02P_1
D12
1
IO_L01N_1
B13
1
IO_L01P_1
C13
No Connect in XC2V80
NC
NC
NC
NC
NC
2
IO_L01N_2
C16
2
IO_L01P_2
D16
2
IO_L02N_2/VRP_2
D14
2
IO_L02P_2/VRN_2
D15
2
IO_L03N_2
E13
2
IO_L03P_2/VREF_2
E14
2
IO_L04N_2
E15
NC
2
IO_L04P_2
E16
NC
2
IO_L06N_2
F13
NC
2
IO_L06P_2
F14
NC
2
IO_L43N_2
F15
NC
NC
2
IO_L43P_2
F16
NC
NC
2
IO_L45N_2
F12
NC
NC
2
IO_L45P_2/VREF_2
G12
NC
NC
2
IO_L91N_2
G13
NC
2
IO_L91P_2
G14
NC
2
IO_L93N_2
G15
NC
2
IO_L93P_2/VREF_2
G16
NC
2
IO_L94N_2
H13
2
IO_L94P_2
H14
2
IO_L96N_2
H15
2
IO_L96P_2
H16
DS031-4 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 4 of 4
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