M306H7MG-XXXFP Datasheet, PDF (94/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
Main clock
1/2 ^f2SIO
f1SIO
1/8
PCLK1=0
PCLK1=1
f1SIO or f2SIO
f8SIO
(UART0)
1/4
f32SIO
RxD0
RxD polarity
reversing circuit
Clock source selection
f1SIO or f2SIO
f8SIO
f32SIO
CLK1 to CLK0
002
012 Internal CKDIR=0
U0BRG
register
102
External
1 / (n0+1)
CKDIR=1
UART reception
1/16
Clock synchronous
type
UART transmission
1/16
Clock synchronous
type
Reception
control circuit
Transmission control
circuit
CLK0
CTS0 / RTS0
Clock synchronous type
(when internal clock is selected)
1/2
CKDIR=0
Clock synchronous type
CKPOL
(when external clock is selected)
Clock synchronous type
CKDIR=1
CLK
(when internal clock is selected)
polarity
reversing
circuit
CTS/RTS selected
CTS/RTS disabled
CRS=1
RTS0
CRS=0
“H”
RCSP=0
CTS/RTS disabled
CRD=1
CTS0
Receive
clock
Transmit
clock
(UART1)
CTS0 from UART1
RCSP=1
CRD=0
RxD1
RxD polarity
reversing circuit
Clock source selection
CLK1 to CLK0
f1SIO or f2SIO
f8SIO
f32SIO
002
012
102
U1BRG
Internal CKDIR=0 _register
1 / (n1+1)
External _CKDIR=1
UART reception
1/16
Clock synchronous
type
UART transmission
1/16
Clock synchronous
type
Reception
control circuit
Transmission
control circuit
CLK1
CTS1 / RTS1/
CTS0/ CLKS1
CKPOL
CLK
polarity
reversing
circuit
Clock output
pin select
CLKMD1=1
CLKMD1=0
CLKMD0=0
Clock synchronous type
1/2
(when internal clock is selected)
CKDIR=0
Clock synchronous type
(when external clock is selected) _CKDIR=1
Clock synchronous type
(when internal clock is selected)
CLKMD0=1
CTS/RTS selected CTS/RTS disabled
CRS=1
RTS1
CRS=0 _{“H”}
CTS/RTS disabled
CRD=1
RCSP=0
CTS1
Receive
clock
Transmit
clock
(UART2)
CRD=0
RCSP=1
CTS0 from UART0
RxD2
RxD polarity
reversing circuit
Clock source selection
CLK1 to CLK0
f1SIO or f2SIO
f8SIO
f32SIO
002
012
102
U2BRG
Internal CKDIR=0 register
1 / (n2+1)
External CKDIR=1
UART reception
1/16
Clock synchronous
type
UART transmission
1/16
Clock synchronous
type
Reception
control circuit
Transmission
control circuit
CLK2
CKPOL
CLK
polarity
reversing
circuit
Clock synchronous type
1/2 ^{(when internal clock is selected)}
CKDIR=0
Clock synchronous type
(when external clock is selected) _CKDIR=1
Clock synchronous type
(when internal clock is selected)
CTS2 / RTS2
CTS/RTS
selected _CRS=1
CRS=0
CTS/RTS disabled
“H”
RTS2
CTS/RTS disabled
CRD=1
CTS2
Receive
clock
Transmit
clock
CRD=0
i = 0 to 2
ni: Values set to the UiBRG register
SMD2 to SMD0, CKDIR: UiMR register's bits
CLK1 to CLK0, CKPOL, CRD, CRS: UiC0 register's bits
CLKMD0, CLKMD1, RCSP: UCON register's bits
Note: UART2 is the N-channel open-drain output. Cannot be set to the CMOS output.
Figure 10.1 UARTi Block Diagram
Transmit/
receive
unit
Transmit/
receive
unit
Transmit/
receive
unit
TxD
polarity
reversing
circuit
TxD
polarity
reversing
circuit
TxD
polarity
reversing
circuit
(Note)
TxD0
TxD1
TxD2
Rev.2.10 Oct 25, 2006 Page 94 of 326
REJ03B0152-0210