M306H7MG-XXXFP Datasheet, PDF (314/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
19. USAGE NOTES
19.5 Precautions for Timers
Precautions for Timer A
19.5.1 Timer A
(1) Timer A (Timer Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to
4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register is modified while the TAiS bit remains “0” (count stops) regardless
whether after reset or not.
(2) While counting is in progress, the counter value can be read out at any time by reading the TAi register.
However, if the counter is read at the same time it is reloaded, the value “FFFF16” is read.
Also, if the counter is read before it starts counting after a value is set in the TAi register while not
counting, the set value is read.
19.5.2 Timer A (Event Counter Mode)
(1) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to
4) register, the TAi register, the UDF register, the ONSF register TAZIE, TA0TGL and TA0TGH bits and
the TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the UDF register, the ONSF register TAZIE, TA0TGL and
TA0TGH bits and the TRGSR register are modified while the TAiS bit remains “0” (count stops)
regardless whether after reset or not.
(2) While counting is in progress, the counter value can be read out at any time by reading the TAi register.
However, “FFFF16” can be read in underflow, while reloading, and “000016” in overflow.
When setting TAi register to a value during a counter stop, the setting value can be read before a counter
starts counting.
19.5.3 Timer A (One-shot Timer Mode)
(1) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to
4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR register before
setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR
register are modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not.
(2) When setting TAiS bit to “0” (count stop), the followings occur:
•A counter stops counting and a content of reload register is reloaded.
•TAiOUT pin outputs “L”.
•After one cycle of the CPU clock, the IR bit of TAiIC register is set to “1” (interrupt request).
(3) Output in one-shot timer mode synchronizes with a count source internally generated. When an external
trigger has been selected, one-cycle delay of a count source as maximum occurs between a trigger input to
TAiIN pin and output in one-shot timer mode.
(4) The IR bit is set to “1” when timer operation mode is set with any of the following procedures:
•Select one-shot timer mode after reset.
•Change an operation mode from timer mode to one-shot timer mode.
•Change an operation mode from event counter mode to one-shot timer mode.
To use the timer Ai interrupt (the IR bit), set the IR bit to “0” after the changes listed above have been
made.
(5) When a trigger occurs, while counting, a counter reloads the reload register to continue counting after
generating a re-trigger and counting down once. To generate a trigger while counting, generate a second
trigger between occurring the previous trigger and operating longer than one cycle of a timer count source.
Rev.2.10 Oct 25, 2006 Page 314 of 326
REJ03B0152-0210