M306H7MG-XXXFP Datasheet, PDF (161/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
11. MULTI-MASTER I²C BUS INTERFACE
• START condition generating procedure using multi-master
FCLR
BTST
JC
BUSFREE:
:
I
5, IICS1
BUSBUSY
(Interrupt disabled)
(BB flag confirming and branch process)
MOV.B
NOP
NOP
NOP
NOP
MOV.B
FSET
BUSBUSY:
FSET
SA, IICS0
#F0H, IICS1
I
:
I
:
(Writing of slave address value <SA>)
(1) (2)
(Trigger of START condition generating)
(Interrupt enabled)
(Interrupt enabled)
(1) Be sure to add NOP instruction × 4 between writing the slave address value and setting trigger of START
condition generating shown the above procedure example.
(2) When using multi-master system, disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts immediately.
When using single-master system, it is not necessary to disable interrupts above.
• RESTART condition generating procedure
MOV.B
NOP
NOP
MOV.B
:
SA, IICS0S
#F0H, IICS1
:
(Writing of slave address value <SA>)
(1)
(Trigger of RESTART condition generating)
(1) Use the I²C transmit buffer register to write the slave address value to the I²C data shift register.
And also, be sure to add NOP instruction × 4.
• Writing to I²C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and TRX bits to
“0” from “1” simultaneously. It is because it may enter the state that the SCL pin is released and the SDA pin is
released after about one machine cycle. Do not execute an instruction to set the MST and TRX bits to “0” from
“1” simultaneously when the PIN bit is “1.” It is because it may become the same as above.
• Process of after STOP condition generating
Do not write data in the I²C data shift register (IICS0) and the I²C status register (IICS1) until the bus busy flag
BB becomes “0” after generating the STOP condition in the master mode. It is because the STOP condition
waveform might not be normally generated. Reading to the above registers do not have the problem.
Rev.2.10 Oct 25, 2006 Page 161 of 326
REJ03B0152-0210