M306H7MG-XXXFP Datasheet, PDF (240/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
14.6 Expansion Register Construction Composition
(1) Acquisition timing
The SLICEON signal is output in the acquisition possible period.
14. EXPANSION FUNCTION
The first field
Vertical blanking erase period pulse
Acquisition possible period
62 2 623 ₆ 24 ₆₂ 5 ₁
2
3
45
6
7
89
1 ^{9 20 21 22} 23 24
The second field
SLICEON output period
310 311 312 313 314 315 316 317 318 319 320 321
331 332 333 334 335 336
The scanning lines number in figure is corresponds to slice RAM.
This is the line to support when the PAL video signal is sliced and setting the expansion registers to
VPS_VP8 to VPS_VP0 (bits 8 to 0 in address 2916) = "416".
Figure 14.11 Expansion register access registers composition
(2) Synchronized signal detection circuit
The number of pulses of the horizontal synchronized signal of a compound video signal is counted during a fixed
period. The horizontal synchronous number of pulses can always be read from an expansion register.
A block diagram is shown in Figure. 14.12.
The arbitration circuit for
expansion registers
Address bus
Data bus
Latch
HOR
Q
T 16bit counter
Possible to count C00016 at maximum.
Figure 14.12 Block diagram of Synchronized detection circuit
Rev.2.10 Oct 25, 2006 Page 240 of 326
REJ03B0152-0210