M306H7MG-XXXFP Datasheet, PDF (123/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
Table 10.13 STSPSEL Bit Functions
Function
Output of SCLi and SDAi pins
Start/stop condition interrupt
request generation timing
STSPSEL = 0
Output of transfer clock and
data
Output of start/stop condition is
accomplished by a program
using ports (not automatically
generated in hardware)
Start/stop condition detection
STSPSEL = 1
Output of a start/stop condition
according to the STAREQ,
RSTAREQ and STPREQ bit
Finish generating start/stop condi-
tion
(1) When slave
CKDIR=1 (external clock)
STSPSEL bit 0
1st 2nd 3rd
SCLi
SDAi
5th 6th 7th 8th 9th bit
Start condition
detection interrupt
Stop condition
detection interrupt
(2) When master
CKDIR=0 (internal clock), CKPH=1 (clock delayed)
STSPSEL bit
SCLi
Set to “1” in
a program
Set to “0” in
a program
1st 2nd 3rd
Set to “1” in
a program
5th 6th 7th 8th 9th bit
Set to “0” in
a program
SDAi
Set STAREQ=
1 (start)
Start condition
detection interrupt
Set STPREQ=
1 (start)
Stop condition
detection interrupt
Figure 10.24 STSPSEL Bit Functions
10.4.3 Arbitration
Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising edge of
SCLi. Use the UiSMR register’s ABC bit to select the timing at which the UiRB register’s ABT bit is updated.
If the ABC bit = 0 (updated bitwise), the ABT bit is set to “1” at the same time unmatching is detected during
check, and is cleared to “0” when not detected. In cases when the ABC bit is set to “1”, if unmatching is
detected even once during check, the ABT bit is set to “1” (unmatching detected) at the falling edge of the clock
pulse of 9th bit. If the ABT bit needs to be updated bytewise, clear the ABT bit to “0” (undetected) after
detecting acknowledge in the first byte, before transferring the next byte.
Setting the UiSMR2 register’s ALS bit to “1” (SDA output stop enabled) causes arbitration-lost to occur, in
which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit is set to “1”
(unmatching detected).
Rev.2.10 Oct 25, 2006 Page 123 of 326
REJ03B0152-0210