M306H7MG-XXXFP Datasheet, PDF (300/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
17. FLASH MEMORY VERSION
17.8 Full Status Check
When an error occurs, the FMR0 register’s FMR06 to FMR07 bits are set to “1”, indicating occurrence of each
specific error. Therefore, execution results can be verified by checking these status bits (full status check). Table
17.6 lists errors and FMR0 register status. Figure 17.12 shows a full status check flowchart and the action to be
taken when each error occurs.
Table 17.6 Errors and FMR0 Register Status
FRM00 register
(status register)
status
FMR07 FMR06
(SR5) (SR4)
1
1
Error
Error occurence condition
Command
• When any command is not written correctly
sequence error • When invalid data was written other than those that can be writ-
ten in the second bus cycle of the Lock Bit Program or Block
Erase command (i.e., other than ‘xxD016’ or ‘xxFF16’) (Note 1)
1
0
Erase error
• When the Block Erase command was executed on locked blocks
(Note 2)
• When the Block Erase command was executed on unlocked
blocks but the blocks were not automatically erased correctly
0
1
Program error • When the Program command was executed on locked blocks
(Note 2)
• When the Program command was executed on unlocked blocks
but the blocks were not automatically programmed correctly.
• When the Lock Bit Program command was executed but not pro-
grammed correctly
Note 1: If "xxFF16" is written by the 2nd bus cycle of these commands, it will become lead array mode and
the command code written by the 1st bus cycle will become invalid simultaneously.
Note 2: When FMR02 bit is "1" (lock bit is invalid), an error is not generated on these conditions.
Rev.2.10 Oct 25, 2006 Page 300 of 326
REJ03B0152-0210