M306H7MG-XXXFP Datasheet, PDF (317/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
19. USAGE NOTES
19.6 Precautions for Serial I/O (Clock-synchronous Serial I/O)
19.6.1 Transmission/reception
With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L”
when the data-receivable status becomes ready, which informs the transmission side that the reception has
become ready. The output level of the RTSi pin goes to “H” when reception starts. So if the RTSi pin is
connected to the CTSi pin on the transmission side, the circuit can transmission and reception data with
consistent timing. With the internal clock, the RTS function has no effect.
19.6.2 Transmission
When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
• The TE bit of UiC1 register= “1” (transmission enabled)
• The TI bit of UiC1 register = “0” (data present in UiTB register)
• If CTS function is selected, input on the CTSi pin = “L”
19.6.3 Reception
(1) In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix
settings for transmission even when using the device only for reception. Dummy data is output to the
outside from the TxDi pin when receiving data.
(2) When an internal clock is selected, set the UiC1 register (i = 0 to 2)’s TE bit to 1 (transmission enabled)
and write dummy data to the UiTB register, and the shift clock will thereby be generated.
When an external clock is selected, set the UiC1 register (i = 0 to 2)’s TE bit to 1 and write dummy data
to the UiTB register, and the shift clock will be generated when the external clock is fed to the CLKi
input pin.
(3) When successively receiving data, if all bits of the next receive data are prepared in the UARTi receive
register while the UiC1 register (i = 0 to 2)’s RE bit = “1” (data present in the UiRB register), an
overrun error occurs and the UiRB register OER bit is set to “1” (overrun error occurred). In this case,
because the content of the UiRB register is indeterminate, a corrective measure must be taken by
programs on the transmit and receive sides so that the valid data before the overrun error occurred will
be retransmitted. Note that when an overrun error occurred, the SiRIC register IR bit does not change
state.
(4) To receive data in succession, set dummy data in the lower-order byte of the UiTB register every time
reception is made.
(5) When an external clock is selected, the conditions must be met while if the CKPOL bit = “0”, the
external clock is in the high state; if the CKPOL bit = “1”, the external clock is in the low state.
•. The RE bit of UiC1 register= “1” (reception enabled)
•. The TE bit of UiC1 register= “1” (transmission enabled)
•. The TI bit of UiC1 register= “0” (data present in the UiTB register)
Rev.2.10 Oct 25, 2006 Page 317 of 326
REJ03B0152-0210