M306H7MG-XXXFP Datasheet, PDF (318/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
19. USAGE NOTES
19.7 Precautions for Serial I/O (UART Mode)
19.7.1 Special Mode 4 (SIM Mode)
A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to “1” (transmission complete)
and U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM mode, be sure to clear the IR
bit to “0” (no interrupt request) after setting these bits.
19.8 Precautions for A/D Converter
(1) Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a
trigger occurs).
(2) When the VCUT bit of ADCON1 register is changed from “0” (Vref not connected) to “1” (Vref
connected), start A/D conversion after passing 1 µs or longer.
(3) To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert
capacitors between the AVCC and analog input pins (ANi (i=0 to 7)) each and the AVSS pin. Similarly,
insert a capacitor between the VCC pin and the VSS pin. Figure 19.2 is an example connection of each pin.
(4) Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input mode).
Also, if the ADCON0 register’s TGR bit = 1 (external trigger), make sure the port direction bit for the
ADTRG pin is set to “0” (input mode).
(5) The φAD frequency must be 10 MHz or less. Without sample-and-hold function, limit the φAD frequency
to 250kHZ or more. With the sample and hold function, limit the φAD frequency to 1MHZ or more.
(6) When changing an A/D operation mode, select analog input pin again in the CH2 to CH0 bits of ADCON0
register and the SCAN1 to SCAN0 bits of ADCON1 register.
(7) If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi
register after completion of A/D conversion, an incorrect value may be stored in the ADi register. This
problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU
clock.
• When operating in one-shot or single-sweep mode
Check to see that A/D conversion is completed before reading the target ADi register. (Check the ADIC
register’s IR bit to see if A/D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
(8) If A/D conversion is forcibly terminated while in progress by setting the ADCON0 register’s ADST bit to
“0” (A/D conversion halted), the conversion result of the A/D converter is indeterminate. The contents of
ADi registers irrelevant to A/D conversion may also become indeterminate. If while A/D conversion is
underway the ADST bit is cleared to “0” in a program, ignore the values of all ADi registers.
Rev.2.10 Oct 25, 2006 Page 318 of 326
REJ03B0152-0210