M306H7MG-XXXFP Datasheet, PDF (100/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
UARTi special mode register 2 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
U0SMR2 to U2SMR2 036E16, 037216, 037616
After reset
X00000002
Bit
symbol
Bit name
Function
RW
IICM2 I²C mode select bit 2
Refer to Table 10.12
RW
CSC Clock-synchronous bit 0 : Disabled
1 : Enabled
RW
SWC ^{SCL wait output bit}
0 : Disabled
1 : Enabled
RW
ALS
SDA output stop bit
0 : Disabled
1 : Enabled
RW
STAC ^{UARTi initialization bit}
0 : Disabled
1 : Enabled
RW
SWC2 SCL wait output bit 2
0: Transfer clock
1: “L” output
RW
SDHI
SDA output disable bit
0: Enabled
1: Disabled (high impedance)
RW
Nothing is assigned. When write, set “0”. When read, its content is
(b7) indeterminate.
UARTi special mode register 3 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0SMR3 to U2SMR3
Address
036D16, 037116, 037516
After reset
000X0X0X2
Bit
symbol
Bit name
Function
RW
Nothing is assigned.
(b0) _{When write, set “0”. When read, its content is indeterminate.}
CKPH Clock phase set bit
0 : Without clock delay
1 : With clock delay
RW
Nothing is assigned.
(b2) _{When write, set “0”. When read, its content is indeterminate.}
NODC Clock output select bit 0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
RW
Nothing is assigned.
(b4) _{When write, set “0”. When read, its content is indeterminate.}
DL0 _{SDAi digital delay}
setup bit
b7 b6 b5
0 0 0 : Without delay
RW
(Note 1, Note 2)
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
DL1
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
RW
1 0 0 : 4 to 5 cycles of UiBRG count source
DL2
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
RW
1 1 1 : 7 to 8 cycles of UiBRG count source
Note 1 : The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I²C mode. In other than I²C
mode, set these bits to “0002” (no delay).
Note 2 : The amount of delay varies with the load on SCLi and SDAi pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.
Figure 10.7 U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers
Rev.2.10 Oct 25, 2006 Page 100 of 326
REJ03B0152-0210