M306H7MG-XXXFP Datasheet, PDF (55/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
6. INTERRUPTS
6.13 Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are
restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar instruction
before executing the REIT instruction
6.14 Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request that has the
highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to ILVL0
bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by
hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 6.8 shows the
priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Reset
NMI
DBC
Watchdog timer
Peripheral function
Single step
Address match
Figure 6.8 Hardware Interrupt Priority
High
Low
6.15 Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those
requested.
Figure 6.9 shows the circuit that judges the interrupt priority level.
Rev.2.10 Oct 25, 2006 Page 55 of 326
REJ03B0152-0210