M306H7MG-XXXFP Datasheet, PDF (106/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
10.2.1 CLK Polarity Select Function
Use the UiC0 register (i = 0 to 2)’s CKPOL bit to select the transfer clock polarity. Figure 10.10 shows the
polarity of the transfer clock.
(1) When the UiC0 register’s CKPOL bit = 0 (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)
CLKi
(Note 2)
TXDi
D0 D1 D2 D3 D4 D5 D6 D7
RXDi
D0 D1 D2 D3 D4 D5 D6 D7
(2) When the UiC0 register’s CKPOL bit = 1 (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock)
CLKi
(Note 3)
TXDi
D0 D1 D2 D3 D4 D5 D6 D7
RXDi
D0 D1 D2 D3 D4 D5 D6 D7
Note 1: This applies to the case where the UiC0 register’s UFORM bit = 0
(LSB first) and UiC1 register's UiLCH bit = 0 (no reverse).
Note 2: When not transferring, the CLKi pin outputs a high signal.
Note 3: When not transferring, the CLKi pin outputs a low signal.
i = 0 to 2
Figure 10.10 Transfer Clock Polarity
10.2.2 LSB First/MSB First Select Function
Use the UiC0 register (i = 0 to 2)’s UFORM bit to select the transfer format. Figure 10.11 shows the transfer
format.
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLKi
TXDi
D0 D1 D2 D3 D4 D5 D6 D7
RXDi
D0 D1 D2 D3 D4 D5 D6 D7
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLKi
TXDi
D7 D6 D5 D4 D3 D2 D1 D0
RXDi
D7 D6 D5 D4 D3 D2 D1 D0
Figure 10.11
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0
(transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock) and the UiC1 register’s
UiLCH bit = 0 (no reverse).
i = 0 to 2
Transfer Format
Rev.2.10 Oct 25, 2006 Page 106 of 326
REJ03B0152-0210