M306H7MG-XXXFP Datasheet, PDF (107/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
10.2.3 Continuous Receive Mode
When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the UiC1 register’s TI bit is set to “0” (data
present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not write
dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the UCON register bit 2 and
bit 3, respectively, and the U2RRM bit is the U2C1 register bit 5.
10.2.4 Serial Data Logic Switching Function
When the UiC1 register (i = 0 to 2)’s UiLCH bit = 1 (reverse), the data written to the UiTB register has its logic
reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB
register. Figure 10.12 shows serial data logic.
(1) When the UiC1 register's UiLCH bit = 0 (no reverse)
Transfer clock ^{“H”}
“L”
TxDi ^{“H”}
(no reverse) _{“L”}
D0 D1 D2 D3 D4 D5 D6 D7
(2) When the UiC1 register's UiLCH bit = 1 (reverse)
Transfer clock ^{“H”}
“L”
TxDi ^{“H”}
(reverse) _{“L”}
D0 D1 D2 D3 D4 D5 D6 D7
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0
(transmit data output at the falling edge and the receive data
taken in at the rising edge of the transfer clock) and the UFORM
bit = 0 (LSB first).
i = 0 to 2
Figure 10.12 Serial Data Logic Switching
10.2.5 Transfer Clock Output From Multiple Pins (UART1)
Use the UCON register’s CLKMD1 to CLKMD0 bits to select one of the two transfer clock output pins. (See
Figure 10.13.) This function can be used when the selected transfer clock for UART1 is an internal clock.
Microcomputer
TXD1 (P67)
CLKS1 (P64)
CLK1 (P65)
IN
CLK
IN
CLK
Transfer enabled
when the UCON
register's
CLKMD0 bit = 0
Transfer enabled
when the UCON
register's
CLKMD0 bit = 1
Note: This applies to the case where the U1MRregister's CKDIR bit
= 0 (internal clock) and the UCON register's CLKMD1 bit = 1
(transfer clock output from multiple pins).
Figure 10.13 Transfer Clock Output From Multiple Pins
Rev.2.10 Oct 25, 2006 Page 107 of 326
REJ03B0152-0210