M306H7MG-XXXFP Datasheet, PDF (90/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
9. TIMERS
9.2.2 Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of other
timers (see Table 9.7) . Figure 9.18 shows TBiMR register in event counter mode.
Table 9.7 Specifications in Event Counter Mode
Item
Specification
Count source
• External signals input to TBiIN pin (i=0 to 5) (effective edge can be selected
in program)
• Timer Bj overflow or underflow (j=i-1, except j=2 if i=0, j=5 if i=3)
Count operation
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio
1/(n+1)
n: set value of TBi register 000016 to FFFF16
Count start condition
Set TBiS bit¹ to “1” (= start counting)
Count stop condition
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function
Count source input
Read from timer
Count value can be read by reading TBi register
Write to timer
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Notes:
1. The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register bit 5 to bit 7.
Timer Bi mode register (i=0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
01
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Address
039B16 to 039D16
035B16 to 035D16
After reset
00XX00002
00XX00002
Bit symbol
Bit name
Function
RW
TMOD0 _{Operation mode select bit} b1 b0
RW
0 1 : Event counter mode
TMOD1
RW
MR0
Count polarity select
b3 b2
bit (Note 1)
0 0 : Counts external signal's
falling edges
RW
0 1 : Counts external signal's
rising edges
MR1
1 0 : Counts external signal's
falling and rising edges
RW
1 1 : Must not be set
MR2
MR3
TB0MR, TB3MR registers
Must be set to “0” in event count mode
RW
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
When write in event counter mode, set to “0”. When read in event
counter mode, its content is indeterminate.
RO
TCK0
Has no effect in event counter mode.
Can be set to “0” or “1”.
RW
TCK1
Event clock select
0 : Input from TBiIN pin (Note 2)
1 : TBj overflow or underflow
(j = i – 1, except j = 2 if i = 0,
RW
j = 5 if i = 3)
Note 1: Effective when the TCK1 bit = “0” (input from TBiIN pin). If the TCK1 bit = “1” (TBj overflow or underflow), these
bits can be set to “0” or “1”.
Note 2: The port direction bit for the TBiIN pin must be set to “0” (= input mode).
Figure 9.18 TBiMR Register in Event Counter Mode
Rev.2.10 Oct 25, 2006 Page 90 of 326
REJ03B0152-0210