M306H7MG-XXXFP Datasheet, PDF (103/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
Table 10.2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register
Bit
UiTB(Note3) 0 to 7
UiRB(Note3) 0 to 7
OER
UiBRG 0 to 7
UiMR(Note3) SMD2 to SMD0
CKDIR
IOPOL
UiC0
CLK1 to CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
UiC1
TE
TI
RE
RI
U2IRS (Note 1)
U2RRM (Note 1)
UiLCH
UiERE
UiSMR 0 to 7
UiSMR2 0 to 7
UiSMR3 0 to 2
NODC
4 to 7
UiSMR4 0 to 7
UCON
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1
RCSP
7
Function
Set transmission data
Reception data can be read
Overrun error flag
Set a transfer rate
Set to “0012”
Select the internal clock or external clock
Set to “0”
Select the count source for the UiBRG register
_______
_______
Select CTS or RTS to use
Transmit register empty flag
_______
_______
Enable or disable the CTS or RTS function
Select TxDi pin output mode (Note 2)
Select the transfer clock polarity
Select the LSB first or MSB first
Set this bit to “1” to enable transmission/reception
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set this bit to “1” to use continuous receive mode
Set this bit to “1” to use inverted data logic
Set to “0”
Set to “0”
Set to “0”
Set to “0”
Select clock output mode
Set to “0”
Set to “0”
Select the source of UART0/UART1 transmit interrupt
Set this bit to “1” to use continuous receive mode
Select the transfer clock output pin when CLKMD1 = 1
Set this bit to “1” to output UART1 transfer clock from two pins
_________
Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin
Set to “0”
Note 1: Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Note 2: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
Note 3: Not all register bits are described above. Set those bits to “0” when writing to the registers in clock
synchronous serial I/O mode.
i=0 to 2
Rev.2.10 Oct 25, 2006 Page 103 of 326
REJ03B0152-0210