M306H7MG-XXXFP Datasheet, PDF (10/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
1. DESCRIPTION
1.6 Memory
Figure 1.4 is a memory map of M306H7MG-XXXFP/MC-XXXFP/FCFP. The address space extends the
1M bytes from address 0000016 to FFFFF16.
The internal ROM is allocated in a lower address direction beginning with address FFFFF16. An internal
ROM of M306H7MC-XXXFP, for instance, is allocated to the addresses from E000016 to FFFFF16.
The fixed interrupt vector table is allocated to the addresses from FFFDC16 to FFFFF16. Therefore, store
the start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 0040016. An internal
RAM of M306H7MC-XXXFP, for instance, is allocated to the addresses from 0040016 to 017FF16. In
addition to storing data, the internal RAM also stores the stack used when calling subroutines and when
interrupts are generated.
SFR is allocated to the addresses from 0000016 to 003FF16. Peripheral function control registers are
located here. Of SFR, any area which has no functions allocated is reserved for future use and cannot
be used by users.
The special page vector table is allocated to the addresses from FFE0016 to FFFDB16. This vector is
used by the JMPS or JSRS instruction. For details, refer to the “M16C/60 and M16C/20 Series Software
Manual.”
In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be
used by users.
0000016
0040016
XXXXX16
SFR
Internal RAM
Internal RAM
Internal ROM
Size Address XXXXX16 Size Address YYYYY16
5K bytes
17FF16
128K bytes
E000016
8K bytes
23FF16
256K bytes
C000016
YYYYY16
FFFFF16
Internal ROM
FFE0016
Special page
vector table
FFFDC16 _{Undefined instruction}
Overflow
BRK instruction
Address match
Single step
Watchdog timer
DBC
FFFFF16
NMI
Reset
Figure 1.4 Memory Map
Rev.2.10 Oct 25, 2006 Page 10 of 326
REJ03B0152-0210