M306H7MG-XXXFP Datasheet, PDF (153/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
11. MULTI-MASTER I²C BUS INTERFACE
(6) I²C status register
The I²C status register controls the I²C-BUS interface status. Bits 0 to 3, 5 are read-only bits and bits 4, 6, 7 can be
read out and written to.
• Bit 0: last receive bit (LRB)
This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is
returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is set to “1.” Except
in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by
executing a write instruction to the I²C data shift register or the I²C transmit buffer register.
• Bit 1: general call detecting flag (AD0)
This bit is set to “1” when a general call∗ whose address data is all “0” is received in the slave mode.
By a general call of the master device, every slave device receives control data after the general call.
The AD0 bit is set to ì0î by detecting the STOP condition or START condition.
∗General call: The master transmits the general call address “0016”to all slaves.
• Bit 2: slave address comparison flag (AAS)
This flag indicates a comparison result of address data.
<<In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following
conditions.>>
• The address data immediately after occurrence of a START condition matches the slave address stored in the
high-order 7 bits of the I²C address register.
• A general call is received.
<<In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following
condition.>>
• When the address data is compared with the I²C address register (8 bits consists of slave address and RBW),
the first bytes match.
<<The state of this bit is changed from “1” to “0” by executing a write instruction to the I²C data shift register or
the I²C transmit buffer register.>>
• Bit 3: arbitration lost∗ detecting flag (AL)
In the master transmission mode, when a device other than the microcomputer sets the SDA to “L,” arbitration is
judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set to “0,” so that
immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to “0.”
When arbitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set.
Consequently, it becomes possible to receive and recognize its own slave address transmitted by another master
device.
<<This bit changes “1” to “0” by writing instruction to I²C data shift register or I²C transmit buffer
register.>>
∗Arbitration lost: The status in which communication as a master is disabled.
Rev.2.10 Oct 25, 2006 Page 153 of 326
REJ03B0152-0210