M306H7MG-XXXFP Datasheet, PDF (124/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
10.4.4 Transfer Clock
Data is transmitted/received using a transfer clock like the one shown in Figure 10.24.
The UiSMR2 register’s CSC bit is used to synchronize the internally generated clock (internal SCLi) and an
external clock supplied to the SCLi pin. In cases when the CSC bit is set to “1” (clock synchronization enabled),
if a falling edge on the SCLi pin is detected while the internal SCLi is high, the internal SCLi goes low, at which
time the UiBRG register value is reloaded with and starts counting in the low-level interval. If the internal SCLi
changes state from low to high while the SCLi pin is low, counting stops, and when the SCLi pin goes high,
counting restarts.
In this way, the UARTi transfer clock is comprised of the logical product of the internal SCLi and SCLi pin
signal. The transfer clock works from a half period before the falling edge of the internal SCLi 1st bit to the
rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock.
The UiSMR2 register’s SWC bit allows to select whether the SCLi pin should be fixed to or freed from low-
level output at the falling edge of the 9th clock pulse.
If the UiSMR4 register’s SCLHI bit is set to “1” (enabled), SCLi output is turned off (placed in the high
impedance state) when a stop condition is detected.
Setting the UiSMR2 register’s SWC2 bit = 1 (0 output) makes it possible to forcibly output a low-level signal
from the SCLi pin even while sending or receiving data. Clearing the SWC2 bit to “0” (transfer clock) allows
the transfer clock to be output from or supplied to the SCLi pin, instead of outputting a low-level signal.
If the UiSMR4 register’s SWC9 bit is set to “1” (SCL hold low enabled) when the UiSMR3 register’s CKPH bit
= 1, the SCLi pin is fixed to low-level output at the falling edge of the clock pulse next to the ninth. Setting the
SWC9 bit = 0 (SCL hold low disabled) frees the SCLi pin from low-level output.
10.4.5 SDA Output
The data written to the UiTB register bit 7 to bit 0 (D7 to D0) is sequentially output beginning with D7.
The ninth bit (D8) is ACK or NACK.
The initial value of SDAi transmit output can only be set when IICM = 1 (I2C mode) and the UiMR register’s
SMD2 to SMD0 bits = ‘0002’ (serial I/O disabled).
The UiSMR3 register’s DL2 to DL0 bits allow to add no delays or a delay of 2 to 8 UiBRG count source clock
cycles to SDAi output.
Setting the UiSMR2 register’s SDHI bit = 1 (SDA output disabled) forcibly places the SDAi pin in the high-
impedance state. Do not write to the SDHI bit synchronously with the rising edge of the UARTi transfer clock.
This is because the ABT bit may inadvertently be set to “1” (detected).
10.4.6 SDA Input
When the IICM2 bit = 0, the 1st to 8th bits (D7 to D0) of received data are stored in the UiRB register bit 7 to bit
0. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit = 1, the 1st to 7th bits (D7 to D1) of received data are stored in the UiRB register bit 6 to bit
0 and the 8th bit (D0) is stored in the UiRB register bit 8. Even when the IICM2 bit = 1, providing the CKPH bit
= 1, the same data as when the IICM2 bit = 0 can be read out by reading the UiRB register after the rising edge
of the corresponding clock pulse of 9th bit.
10.4.7 ACK and NACK
If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and the ACKC
bit in the UiSMR4 register is se to “1” (ACK data output), the value of the ACKD bit in the UiSMR4 register is
output from the SDAi pin.
If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising edge of
the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDAi pin is low at the rising
edge of the 9th bit of transmit clock pulse.
If ACKi is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an
acknowledge.
Rev.2.10 Oct 25, 2006 Page 124 of 326
REJ03B0152-0210