M306H7MG-XXXFP Datasheet, PDF (316/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
19. USAGE NOTES
Precautions for Timer B
19.5.5 Timer B (Timer Mode)
(1) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i =
0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1”
(count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not.
(2) A value of a counter, while counting, can be read in TBi register at any time. “FFFF16” is read while
reloading. Setting value is read between setting values in TBi register at count stop and starting a
counter.
19.5.6 Timer B (Event Counter Mode)
(1) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i =
0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1”
(count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not.
(2) The counter value can be read out on-the-fly at any time by reading the TBi register. However, if this
register is read at the same time the counter is reloaded, the read value is always “FFFF16.” If the TBi
register is read after setting a value in it while not counting but before the counter starts counting, the
read value is the one that has been set in the register.
19.5.7 Timer B (Pulse Period/pulse Width Measurement Mode)
(1) The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 5) register
before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not. To clear the MR3 bit to “0” by writing to the TBiMR register while
the TBiS bit = “1” (count starts), be sure to write the same value as previously written to the TM0D0,
TM0D1, MR0, MR1, TCK0 and TCK1 bits and a 0 to the MR2 bit.
(2) The IR bit of TBiIC register (i=0 to 5) goes to “1” (interrupt request), when an effective edge of a
measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be determined
by use of the MR3 bit of TBiMR register within the interrupt routine.
(3) If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse input
and a timer overflow occur at the same time, use another timer to count the number of times timer B has
overflowed.
(4) To set the MR3 bit to “0” (no overflow), set TBiMR register with setting the TBiS bit to “1” and
counting the next count source after setting the MR3 bit to “1” (overflow).
(5) Use the IR bit of TBiIC register to detect only overflows. Use the MR3 bit only to determine the
interrupt factor within the interrupt routine.
(6) When a count is started and the first effective edge is input, an indeterminate value is transferred to the
reload register. At this time, timer Bi interrupt request is not generated.
(7) A value of the counter is indeterminate at the beginning of a count. MR3 may be set to “1” and timer Bi
interrupt request may be generated between a count start and an effective edge input.
(8) For pulse width measurement, pulse widths are successively measured. Use program to check whether
the measurement result is an “H” level width or an “L” level width.
Rev.2.10 Oct 25, 2006 Page 316 of 326
REJ03B0152-0210