M306H7MG-XXXFP Datasheet, PDF (112/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
(1) Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked.
Tc
The transfer clock starts as the transfer starts immediately CTSi changes to “L”.
Transfer clock
UiC1 register
TE bit
“1”
“0”
UiC1 register
TI bit
“1”
“0”
“H”
CTSi
“L”
TxDi
UiC0 register
“1”
TXEPT bit
“0”
SiTIC register
“1”
IR bit
“0”
Write data to the UiTB register
Transferred from UiTB register to UARTi transmit register
Start
bit
Parity Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Stopped pulsing
because the TE bit
= “0”
ST D0 D1
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set
as follows:
• UiMR register PRYE bit = 1 (parity enabled)
• UiMR register STPS bit = 0 (1 stop bit)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
• UiRS bit = 1 (an interrupt request occurs when transmit completed):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
i: 0 to 2
(2) Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
“1”
UiC1 register
TE bit
“0”
UiC1 register
“1”
TI bit
“0”
TxDi
UiC0 register
“1”
TXEPT bit
“0”
SiTIC register
“1”
IR bit
“0”
Write data to the UiTB register
Start
bit
Stop Stop
bit bit
Transferred from UiTB register to UARTi
transmit register
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP
ST D0 D1
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
as follows:
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
• UiMR register PRYE bit = 0 (parity disabled)
fEXT : frequency of UiBRG count source (external clock)
• UiMR register STPS bit = 1 (2 stop bits)
• UiC0 register CRD bit = 1 (CTS/RTS disabled)
• UiRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty):
n : value set to UiBRG
i: 0 to 2
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Figure 10.15 Transmit Operation
Rev.2.10 Oct 25, 2006 Page 112 of 326
REJ03B0152-0210