M306H7MG-XXXFP Datasheet, PDF (160/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
11. MULTI-MASTER I²C BUS INTERFACE
S Slave address R/W A
Data
A
Data A/A P
7 bits
"0"
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
S Slave address R/W A Data
A Data
AP
7 bits
"1"
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
1st 7 bits
R/W
A
Slave address
2nd byte
A
Data
A Data A/A P
7 bits
"0"
8 bits
1 to 8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
1st 7 bits
R/W A
Slave address
2nd byte
Slave address
A Sr 1st 7 bits
7 bits
"0"
8 bits
7 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
R/W A
Data
A
Data
A
P
"1"
1 to 8 bits
1 to 8 bits
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W :Read/Write bit
From master to slave
From slave to master
Figure 11.13 Address data communication format
(13) Precautions when using multi-master I²C-BUS interface
• BCLK operation mode
Select the no-division mode.
• Used instructions
Specify byte (.B) as data size to access multi-master I²C-BUS interface i-related registers.
• Read-modify-write instruction
The precautions when the read-modify-write instruction such as BSET, BCLR etc. is executed for each register of
the multi-master I²C-BUS interface are described below.
• I²C data shift register (IICS0)
When executing the read-modify-write instruction for this register during transfer, data may become a value
not intended.
• I²C address register (IICS0D)
When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may
become a value not intended. It is because hardware changes the read/write bit (RBW) at the above timing.
• I²C status register (IICS1)
Do not execute the read-modify-write instruction for this register because all bits of this register are changed
by hardware.
• I²C control register (IICS1D)
When the read-modify-write instruction is executed for this register at detecting the START condition or at
completing the byte transfer, data may become a value not intended. Because hardware changes the bit
counter (BC0−BC2) at the above timing.
• I²C clock control register (IICS2)
The read-modify-write instruction can be executed for this register.
• I²C port selection register (IICS2D)
Since the read value of high-order 4 bits is indeterminate, the read-modify-write instruction cannot be used.
• I²C transmit buffer register (IICS0S)
Since the value of all bits is indeterminate, the read-modify-write instruction cannot be used.
Rev.2.10 Oct 25, 2006 Page 160 of 326
REJ03B0152-0210