M306H7MG-XXXFP Datasheet, PDF (53/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
6. INTERRUPTS
6.12 Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG register, 16
bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure 6.6 shows the stack
status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use the PUSHM
instruction, and all registers except SP can be saved with a single instruction.
Address
Stack
MSB
LSB
m–4
m–3
m–2
m–1
m
Content of previous stack
m + 1 ^{Content of previous stack}
[SP]
SP value before
interrupt occurs
Address
Stack
MSB
LSB
m–4
m–3
m–2
PC L
PC M
FLGL
[SP]
New SP value
m–1
FLGH
PCH
m
Content of previous stack
m + 1 Content of previous stack
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
Figure 6.6 Stack Status Before and After Acceptance of Interrupt Request
Rev.2.10 Oct 25, 2006 Page 53 of 326
REJ03B0152-0210