M306H7MG-XXXFP Datasheet, PDF (132/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
(1) UiSMR register ABSCS bit (bus collision detect sampling clock select)
(i=0 to 2)
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
Transfer clock
TxDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
RxDi
Input to TAjIN
Timer Aj
If ABSCS=1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
Timer Aj: timer A3 when UART0; timer A4 when UART1; timer A0 when UART2
(2) UiSMR register ACSE bit (auto clear of transmit enable bit)
Transfer clock
TxDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
RxDi
UiBCNIC register
IR bit (Note)
UiC1 register
TE bit
Note: BCNIC register when UART2.
If ACSE bit = 1 (automatically
clear when bus collision occurs),
the TE bit is cleared to “0”
(transmission disabled) when
the UiBCNIC register’s IR bit = 1
(unmatching detected).
(3) UiSMR register SSS bit (Transmit start condition select ⁾
If SSS bit = 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
TxDi
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge (Note 1) of RxDi
CLKi
TxDi
(Note 2)
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
RxDi
Note 1: The falling edge of RxDi when IOPOL=0; the rising edge of RxDi when IOPOL =1.
Note 2: The transmit condition must be met before the falling edge (Note 1) of RxD.
This diagram applies to the case where IOPOL=1 (reversed).
Figure 10.29 Bus Collision Detect Function-Related Bits
Rev.2.10 Oct 25, 2006 Page 132 of 326
REJ03B0152-0210