M306H7MG-XXXFP Datasheet, PDF (148/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
11. MULTI-MASTER I²C BUS INTERFACE
(3) I²C address register
The I²C address register consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave
address written in this register is compared with the address data to be received immediately after the START
condition are detected.
• Bit 0: read/write bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode, the first address
data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I²C address register.
The RBW bit is cleared to “0” automatically when the stop condition is detected.
• Bits 1 to 7: slave address (SAD0 to SAD6)
These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the
address data transmitted from the master is compared with the contents of these bits.
I²C address register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IIC0S0D
Address
02E116
When reset
0016
Bit Symbol
Bit name
RBW
Read/write bit
SAD0
SAD1
SAD2
SAD3
SAD4
SAD5
SAD6
Slave address
Function
RW
<Only in 10-bit addressing (in slave) mode> _RW
The last significant bit of address data is
compared.
0 : Wait the first byte of slave address
after START condition
(read state)
1 : Wait the first byte of slave address
after RESTART condition
(write state)
<In both modes>
The address data is compared.
RW
Figure 11.5 I²C address register
Rev.2.10 Oct 25, 2006 Page 148 of 326
REJ03B0152-0210