M306H7MG-XXXFP Datasheet, PDF (126/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
10.5 Special Mode 2
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable.
Table 10.14 lists the specifications of Special Mode 2. Table 10.15 lists the registers used in Special Mode 2 and the
register values set. Figure 10.25 shows communication control example for Special Mode 2.
Table 10.14 Special Mode 2 Specifications
Item
Specification
Transfer data format
• Transfer data length: 8 bits
Transfer clock
• Master mode
UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• Slave mode
CKDIR bit = “1” (external clock selected) : Input from CLKi pin
Transmit/receive control
Controlled by input/output ports
Transmission start condition
• Before transmission can start, the following requirements must be met (Note 1)
_ _{The TE bit of UiC1 register= 1 (transmission enabled)}
_ _{The TI bit of UiC1 register = 0 (data present in UiTB register)}
Reception start condition
Interrupt request
generation timing
• Before reception can start, the following requirements must be met (Note 1)
_ _{The RE bit of UiC1 register= 1 (reception enabled)}
_ _{The TE bit of UiC1 register= 1 (transmission enabled)}
_ _{The TI bit of UiC1 register= 0 (data present in the UiTB register)}
• For transmission, one of the following conditions can be selected
_ _{The UiIRS bit of UiC1 register = 0 (transmit buffer empty): when transferring data}
from the UiTB register to the UARTi transmit register (at start of transmission)
_ _{The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from}
the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
Select function
• Clock phase setting
Selectable from four combinations of transfer clock polarities and phases
Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock),
the external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low
state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does
not change.
Rev.2.10 Oct 25, 2006 Page 126 of 326
REJ03B0152-0210