M306H7MG-XXXFP Datasheet, PDF (122/329 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER

M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
10.4.1 Detection of Start and Stop Condtion
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDAi pin changes state from high to low
while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated when the SDAi
pin changes state from low to high while the SCLi pin is in the high state.
Because the start and stop condition-detected interrupts share the interrupt control register and vector, check the
UiSMR register’s BBS bit to determine which interrupt source is requesting the interrupt.
3 to 6 cycles < duration for setting-up (Note)
3 to 6 cycles < duration for holding (Note)
SCLi
SDAi
(Start condition)
SDA i
(Stop condition)
Duration for
setting up
Duration for
holding
i = 0 to 2
Note: When the PCLKR register's PCLK1 bit = 1, this is the cycle number of
f1SIO, and the PCLK1 bit = 0, this is the cycle number of f2SIO.
Figure 10.23 Detection of Start and Stop Condition
10.4.2 Output of Start and Stop Condition
A start condition is generated by setting the UiSMR4 register (i = 0 to 2)’s STAREQ bit to “1” (start).
A restart condition is generated by setting the UiSMR4 register’s RSTAREQ bit to “1” (start).
A stop condition is generated by setting the UiSMR4 register’s STPREQ bit to “1” (start).
The output procedure is described below.
Set the STAREQ bit, RSTAREQ bit or STPREQ bit to “1” (start).
Set the STSPSEL bit in the UiSMR4 register to “1” (output).
The function of the STSPSEL bit is shown in Table 10.13 and Figure 10.24.
Rev.2.10 Oct 25, 2006 Page 122 of 326
REJ03B0152-0210